Verilog 進擊之路 - 夯實基礎第一節之結構化設計
隨著數字電路設計的復雜化和專業化，傳統的電路設計逐漸沒落，Verilog HDL逐漸走入歷史舞臺，好多人并不是不會Verilog，而是缺乏細致的了解，最近一直在看 A Guide to Digital Deisgn and Synthesis 這本書，感覺許多的疑點得到解決，正好分享出來共勉，
對設計者來講，最重要的是如何實作設計和優化設計，如下是 A typical design flow.
- specifications are written first. specificitions 簡要描述了設計電路的function, interface, overall architecture.
- a behavioral description 來分析設計電路的function, peoformance,compliance to standards and high-level issues.
- behavioral description converted to RTL description.
- RTL description converted to gate-level netlist by logic synthesis tools.
- The netlist is input to an automatic place and route tool, which creats a layout.
在進行Verilog design時，必須follow design methodology and basic hierarchical modeling.
1.Design methodology: a combination of top-down and bottom-up. 先構建設計的架構，進行top_level and sub_block的邏輯關系實作，然后在sub_block中build leaf cell and optimized circuits in cell，從而實作top and bottom 的同時設計.
2. Basic hierarchical modeling: a module is the basic buliding block in verilog. 共有四個design level可以使用，behavioral level dataflow level gate level switch level.
3. Test bench include stimulus/monitor and design blocks,搭建仿真環境也要follow the design rules.
本次重點是了解一個verilog design的層次化結構是如何展開的，下節將會闡述作為 basic block 的 module framework是如何實作的.
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標籤：Verilog
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