Dff
這一節終于開始時序電路了，首先是一個用的最多的D觸發器，
module top_module ( input clk, // Clocks are used in sequential circuits input d, output reg q );// // Use a clocked always block // copy d to q at every positive edge of clk // Clocked always blocks should use non-blocking assignments always@(posedge clk) begin q <= d; end endmodule
Dff8
8位D觸發器，寫法和上一題是一樣的，
module top_module ( input clk, input [7:0] d, output [7:0] q ); always@(posedge clk) begin q <= d; end endmodule
Dff8r
帶同步高電平復位的D觸發器，
module top_module ( input clk, input reset, // Synchronous reset input [7:0] d, output [7:0] q ); always@(posedge clk) begin if(reset) q <= 'd0; else q <= d; end endmodule
Dff8p
注意這道題觸發器是下降沿觸發，
module top_module ( input clk, input reset, input [7:0] d, output [7:0] q ); always@(negedge clk) begin if(reset) q <= 'h34; else q <= d; end endmodule
Dff8ar
這道題是異步復位，把areset寫在敏感事件串列即可，
module top_module ( input clk, input areset, // active high asynchronous reset input [7:0] d, output [7:0] q ); always@(posedge clk or posedge areset) begin if(areset) q <= 'd0; else q <= d; end endmodule
Dff16e
這題多了一個位元組使能信號，只有對應的位元組使能才能寫入，否則維持當前的值，
module top_module ( input clk, input resetn, input [1:0] byteena, input [15:0] d, output [15:0] q ); always@(posedge clk) begin if(~resetn) q <= 'd0; else q <= {byteena[1]?d[15:8]:q[15:8],byteena[0]?d[7:0]:q[7:0]}; end endmodule
Exams/m2014 q4a
這題要求使用一個latch，latch是電平觸發的觸發器，當ena信號為高電平時輸入會傳遞給輸出，這樣的缺點是毛刺（glitch）會逐級傳遞，所以應盡量避免綜合出不必要的latch，這一點在前面if和case陳述句中提到過，
提示中告訴了這里應該使用非阻塞賦值，因為其仍然是時序電路，
module top_module ( input d, input ena, output q); always@(*) begin if(ena) q<=d; end endmodule
Exams/m2014 q4b
module top_module ( input clk, input d, input ar, // asynchronous reset output q); always@(posedge clk or posedge ar) begin if(ar) q <= 'd0; else q <= d; end endmodule
Exams/m2014 q4c
總放些重復的題有點浪費時間，，，
module top_module ( input clk, input d, input r, // synchronous reset output q); always@(posedge clk) begin if(r) q <= 'd0; else q <= d; end endmodule
Exams/m2014 q4d
module top_module ( input clk, input in, output out); always@(posedge clk) begin out <= in^out; end endmodule
Mt2015 muxdff
這道題只要寫出一個子模塊即可，
module top_module ( input clk, input L, input r_in, input q_in, output reg Q); always@(posedge clk) begin Q <= L?r_in:q_in; end endmodule
Exams/2014 q4a
同樣也是寫一個子模塊，
module top_module ( input clk, input w, R, E, L, output Q ); always@(posedge clk) begin Q <= L?R:(E?w:Q); end endmodule
Exams/ece241 2014 q4
根據RTL視圖直接寫代碼就可以了，
module top_module ( input clk, input x, output z ); reg [2:0]Q=3'd0; always@(posedge clk) begin Q[0] <= x^Q[0]; Q[1] <= x&~Q[1]; Q[2] <= x|~Q[2]; end assign z=~|Q; endmodule
Exams/ece241 2013 q7
使用verilog實作一個JK觸發器，
module top_module ( input clk, input j, input k, output reg Q); always@(posedge clk) begin case({j,k}) 2'b00:Q<=Q; 2'b01:Q<=1'b0; 2'b10:Q<=1'b1; 2'b11:Q<=~Q; endcase end endmodule
Edgedetect
用了兩個always，其實和答案是一樣的，
module top_module ( input clk, input [7:0] in, output reg[7:0] pedge ); reg [7:0] in_r; always@(posedge clk) begin in_r <= in; end always@(posedge clk) pedge <= in&~in_r; endmodule
Edgedetect2
和上一題思路是一樣的，區別是邏輯改為異或，
module top_module ( input clk, input [7:0] in, output reg[7:0] anyedge ); reg [7:0] in_r; always@(posedge clk) begin in_r <= in; anyedge <= in_r^in; end endmodule
Edgecapture
capture和detect區別：capture會保持1，直到reset，
out <= (~in&in_r)|out;代表只有1會傳遞到out，從而達到保持的作用，
module top_module ( input clk, input reset, input [31:0] in, output reg[31:0] out ); reg [31:0] in_r; always@(posedge clk) begin in_r <= in; if(reset) out <= 'd0; else if(~in&in_r) out <= (~in&in_r)|out; end endmodule
Dualedge
要求寫一個雙邊沿觸發器，題目已經告訴了@(posedge clk or negedge clk)的寫法是不被允許的，
這題確實沒想到好的方法，我的寫法可能會產生毛刺，因為在邊沿的時候q_p和q_n需要時間跳變，這個時候輸出就可能有問題，當然，這樣仿真還是能通過的，但實際電路中不能這樣寫，
題目給的答案非常巧妙，上升沿時p變為d^n，所以輸出q = (p^n) = (d^n^n) = d，下降沿同理，
我的答案：
module top_module ( input clk, input d, output q ); reg q_p,q_n; always@(posedge clk) q_p <= d; always@(negedge clk) q_n <= d; assign q = clk?q_p:q_n; endmodule
標準答案：
module top_module( input clk, input d, output q); reg p, n; // A positive-edge triggered flip-flop always @(posedge clk) p <= d ^ n; // A negative-edge triggered flip-flop always @(negedge clk) n <= d ^ p; // Why does this work? // After posedge clk, p changes to d^n. Thus q = (p^n) = (d^n^n) = d. // After negedge clk, n changes to d^p. Thus q = (p^n) = (p^d^p) = d. // At each (positive or negative) clock edge, p and n FFs alternately // load a value that will cancel out the other and cause the new value of d to remain. assign q = p ^ n; // Can't synthesize this. /*always @(posedge clk, negedge clk) begin q <= d; end*/ endmodule
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標籤：Verilog
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