【HDLBits刷題筆記】13 Finite State Machines-有解無憂

Fsm1

這里需要實作一個簡單的摩爾狀態機，即輸出只與狀態有關的狀態機，

我這里代碼看上去比長一點，答案用的case和三目運算子，結果是一樣的，

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;

    always @(*) begin    // This is a combinational always block
        if(state ==A)begin
            if(in==1)
                next_state=A;
            else
                next_state=B;
        end
        else if(state ==B)begin
            if(in==1)
                next_state=B;
            else
                next_state=A;
        end        
    end

    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        if(areset)
            state <= B;
        else 
            state <= next_state;
    end

    // Output logic
    assign out = (state == B);

endmodule

Fsm1s

和上一題是一樣的，只不過換成了同步復位，

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  

    // Fill in state name declarations

    reg present_state, next_state;
    parameter A=0, B=1; 

    always @(posedge clk) begin
        if (reset) begin  
            present_state <= B;
        end else begin
            // State flip-flops
            present_state <= next_state;   
        end
    end
    
    always@(*)
    begin
        case (present_state)
            A:next_state=in?A:B;
            B:next_state=in?B:A;
        endcase 
    end
    
    assign out = (present_state == B);

endmodule

Fsm2

這里是一個JK觸發器，

module top_module(
    input clk,
    input areset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin
        case(state)
            OFF:next_state=j?ON:OFF;
            ON:next_state=k?OFF:ON;
        endcase
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)
            state <= OFF;
        else
            state <= next_state;
    end

    // Output logic
    assign out = (state == ON);

endmodule

Fsm2s

同樣是異步改成同步就可以了，

module top_module(
    input clk,
    input reset,    // Synchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin
        case(state)
            OFF:next_state=j?ON:OFF;
            ON:next_state=k?OFF:ON;
        endcase
    end

    always @(posedge clk) begin
        if(reset)
            state <= OFF;
        else
            state <= next_state;
    end

    // Output logic
    assign out = (state == ON);

endmodule

Fsm3comb

這道題只需要實作狀態轉換邏輯和輸出邏輯，狀態轉換的時序邏輯不需要實作，

module top_module(
    input in,
    input [1:0] state,
    output [1:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: next_state = f(state, in)
    always@(*)
    begin
        case(state)
            A:next_state=in?B:A;
            B:next_state=in?B:C;
            C:next_state=in?D:A;
            D:next_state=in?B:C;
        endcase
    end

    // Output logic:  out = f(state) for a Moore state machine
    assign out=(state==D);

endmodule

Fsm3onehot

這道題要求使用獨熱碼，即只有一個1的編碼，

這里提到了一個概念"derive equations by inspection"，指通過某一個位就可以判斷當前狀態，例如可以用state[0]判斷當前狀態是否為A，這樣可以簡化狀態轉換邏輯，

module top_module(
    input in,
    input [3:0] state,
    output [3:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: Derive an equation for each state flip-flop.
    assign next_state[A] = (state[A]&~in)|(state[C]&~in);
    assign next_state[B] = (state[A]&in)|(state[B]&in)|(state[D]&in);
    assign next_state[C] = (state[B]&~in)|(state[D]&~in);
    assign next_state[D] = (state[C]&in);

    // Output logic: 
    assign out = state[D];

endmodule

Fsm3

狀態轉換邏輯在前面已經實作了，這里只需要實作狀態轉換暫存器和輸出暫存器，

module top_module(
    input clk,
    input in,
    input areset,
    output out); //
    reg [1:0]state,next_state;
    // State transition logic
    parameter A=0, B=1, C=2, D=3;
    always@(*)
    begin
        case(state)
            A:next_state=in?B:A;
            B:next_state=in?B:C;
            C:next_state=in?D:A;
            D:next_state=in?B:C;
        endcase
    end
    // State flip-flops with asynchronous reset
    always@(posedge clk or posedge areset)
    begin
        if(areset)
            state <= A;
        else 
            state <= next_state;
    end
    // Output logic
    assign out=(state==D);
endmodule

Fsm3s

把上一題的異步復位改成同步復位，

module top_module(
    input clk,
    input in,
    input reset,
    output out); //
    reg [1:0]state,next_state;
    // State transition logic
    parameter A=0, B=1, C=2, D=3;
    always@(*)
    begin
        case(state)
            A:next_state=in?B:A;
            B:next_state=in?B:C;
            C:next_state=in?D:A;
            D:next_state=in?B:C;
        endcase
    end
    // State flip-flops with asynchronous reset
    always@(posedge clk)
    begin
        if(reset)
            state <= A;
        else 
            state <= next_state;
    end
    // Output logic
    assign out=(state==D);
endmodule

Exams/ece241 2013 q4

又是一道正確率十幾的題目，，

fr1、fr2、fr3結果輸出可以直接根據題目給的表得出，dfr需要仔細考慮一下，題目的意思是如果之前的水位比現在的水位低，那么就打開dfr，這里的之前并不是指一個時鐘的之前，所以當狀態不變的時候不需要改變dfr，不過我這種寫法就不是嚴格的摩爾狀態機了，因為我在一個時序邏輯中同時使用了state和next_state做對比，

題目給的答案通過六個狀態來給出輸出，感徑訓是有點復雜的，

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output reg dfr
); 
    parameter A=0,B=1,C=2,D=3;
    reg[1:0]state,next_state;
    always@(posedge clk)
    begin
        if(reset)
            state <= A;
        else
            state <= next_state;
    end
    
    always@(*)
    begin
        next_state = A;
        case(s)
            3'b111:next_state = D;
            3'b011:next_state = C;
            3'b001:next_state = B;
            3'b000:next_state = A;
        endcase
    end
    
    always@(posedge clk)
    begin
        if(reset)
            dfr <= 1;
        else if(next_state<state)
            dfr <= 1;
        else if(next_state>state)
            dfr <= 0;
    end
    assign fr3=(state==A);
    assign fr2=(state==A)||(state==B);
    assign fr1=(state==A)||(state==B)||(state==C);
    
endmodule

Lemmings1

這道題要求用有限狀態機描述游戲Lemmings中的角色，角色將在撞到障礙物時改變方向，

題目已經把狀態機和代碼框架都給出來了，只要補充關鍵部分即可，

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    output walk_left,
    output walk_right); //  

    parameter LEFT=0, RIGHT=1;
    reg state, next_state;

    always @(*) begin
        // State transition logic
        case(state)
            LEFT:next_state=bump_left?RIGHT:LEFT;
            RIGHT:next_state=bump_right?LEFT:RIGHT;
        endcase
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)
            state <= LEFT;
        else
            state <= next_state;
    end

    // Output logic
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);

endmodule

Lemmings2

相比上一題多了一個FALL的狀態，要求FALL之后還要恢復之前的方向，所以這里增加一個狀態是不夠的，至少要增加兩個狀態之后才能使FALL之后恢復原來的狀態，

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 
    
    parameter LEFT=0, RIGHT=1,FALL_L=2,FALL_R=3;
    reg [1:0]state, next_state;

    always @(*) begin
        // State transition logic
        case(state)
            LEFT:next_state=ground?(bump_left?RIGHT:LEFT):FALL_L;
            RIGHT:next_state=ground?(bump_right?LEFT:RIGHT):FALL_R;
            FALL_L:next_state=ground?LEFT:FALL_L;
            FALL_R:next_state=ground?RIGHT:FALL_R;
        endcase
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)
            state <= LEFT;
        else
            state <= next_state;
    end

    // Output logic
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah = (state == FALL_L)||(state == FALL_R);

endmodule

Lemmings3

根據題目給的題目給的狀態轉換表，還是比較好寫的，

直接在上一題代碼基礎上改的，越改越長，

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 

    parameter LEFT=0, RIGHT=1,FALL_L=2,FALL_R=3,DIG_L=4,DIG_R=5;
    reg [2:0]state, next_state;

    always @(*) begin
        // State transition logic
        case(state)
            LEFT:next_state=ground?(dig?DIG_L:(bump_left?RIGHT:LEFT)):FALL_L;
            RIGHT:next_state=ground?(dig?DIG_R:(bump_right?LEFT:RIGHT)):FALL_R;
            FALL_L:next_state=ground?LEFT:FALL_L;
            FALL_R:next_state=ground?RIGHT:FALL_R;
            DIG_L:next_state=ground?DIG_L:FALL_L;
            DIG_R:next_state=ground?DIG_R:FALL_R;
        endcase
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)
            state <= LEFT;
        else
            state <= next_state;
    end

    // Output logic
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah = (state == FALL_L)||(state == FALL_R);
    assign digging = (state == DIG_L)||(state == DIG_R);
endmodule

Lemmings4

當Lemmings 下落超過20個時鐘周期會摔死，注意！Lemmings 不會在半空中摔死，不能以20個周期作為判別條件，而要以到ground時的時鐘周期數來計算，

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 

    parameter LEFT=0, RIGHT=1,FALL_L=2,FALL_R=3,DIG_L=4,DIG_R=5,SPLAT=6;
    reg [2:0]state, next_state;
    reg [7:0]fall_cnt;
    always@(posedge clk , posedge areset)
    begin
        if(areset)
            fall_cnt <= 'd0;
        else if((state == FALL_L)||(state == FALL_R))
            fall_cnt <= (fall_cnt>=20)?fall_cnt:fall_cnt+1'b1;
        else
            fall_cnt <= 'd0;
    end

    always @(*) begin
        // State transition logic
        case(state)
            LEFT:next_state=ground?(dig?DIG_L:(bump_left?RIGHT:LEFT)):FALL_L;
            RIGHT:next_state=ground?(dig?DIG_R:(bump_right?LEFT:RIGHT)):FALL_R;
            FALL_L:next_state=ground?((fall_cnt==20)?SPLAT:LEFT):FALL_L;
            FALL_R:next_state=ground?((fall_cnt==20)?SPLAT:RIGHT):FALL_R;
            DIG_L:next_state=ground?DIG_L:FALL_L;
            DIG_R:next_state=ground?DIG_R:FALL_R;
            SPLAT:next_state=SPLAT;
            default:next_state='dx;
        endcase
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)
            state <= LEFT;
        else
            state <= next_state;
    end

    // Output logic
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah = (state == FALL_L)||(state == FALL_R);
    assign digging = (state == DIG_L)||(state == DIG_R);
endmodule

一次過，完美，今天就做到這里了，這一節題目有點多，有些題還有些復雜，估計還要再寫兩天了，

Fsm onehot

看著簡單，但得找對思路，一開始我用的always@(*)并且標注出了S9~S0，但是由于該測驗還會輸入非獨熱碼，會導致輸出也并非全是獨熱碼，所以要按照出題者的意圖，直接將每一位作為一個狀態直接進行判斷，

module top_module(
    input in,
    input [9:0] state,
    output [9:0] next_state,
    output out1,
    output out2);
    
    assign next_state[0]=~in&&(state[4:0]||state[9:7]);
    assign next_state[1]=in&&(state[0]||state[9:8]);
    assign next_state[2]=in&&state[1];
    assign next_state[3]=in&&state[2];
    assign next_state[4]=in&&state[3];
    assign next_state[5]=in&&state[4];
    assign next_state[6]=in&&state[5];
    assign next_state[7]=in&&state[7:6];
    assign next_state[8]=~in&&state[5];
    assign next_state[9]=~in&&state[6];
    
    assign out1=state[8]|state[9];
    assign out2=state[7]|state[9];
    
endmodule

Fsm ps2

ps/2是早期滑鼠和鍵盤的介面，現在已經基本被USB取代，

這道題只需要通過in[3]來判斷資料傳輸什么時候結束即可，

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output done); //

    parameter BYTE1=0,BYTE2=1,BYTE3=2,DONE=3;
    reg[1:0]state,next_state;
    
    // State transition logic (combinational)
    always@(*)
    begin
        case(state)
            BYTE1:next_state=in[3]?BYTE2:BYTE1;
            BYTE2:next_state=BYTE3;
            BYTE3:next_state=DONE;
            DONE:next_state=in[3]?BYTE2:BYTE1;
        endcase
    end
    // State flip-flops (sequential)
    always@(posedge clk)
    begin
        if(reset)
            state <= BYTE1;
        else 
            state <= next_state;
    end
    // Output logic
    assign done=(state==DONE);

endmodule

Fsm ps2data

在上一題的基礎上增加一個存盤資料的功能.

注意，由于這里狀態DONE的時候下一個狀態直接就是BYTE2了，所以在DONE的時候就可以存盤BYTE1了，

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output reg[23:0] out_bytes,
    output done); //

    // FSM from fsm_ps2
    parameter BYTE1=0,BYTE2=1,BYTE3=2,DONE=3;
    reg[1:0]state,next_state;
    
    // State transition logic (combinational)
    always@(*)
    begin
        case(state)
            BYTE1:next_state=in[3]?BYTE2:BYTE1;
            BYTE2:next_state=BYTE3;
            BYTE3:next_state=DONE;
            DONE:next_state=in[3]?BYTE2:BYTE1;
        endcase
    end
    // State flip-flops (sequential)
    always@(posedge clk)
    begin
        if(reset)
            state <= BYTE1;
        else 
            state <= next_state;
    end
    // Output logic
    assign done=(state==DONE);
    // New: Datapath to store incoming bytes.
    always@(posedge clk)
    begin
        if(reset)
            out_bytes <= 'd0;
        else begin
            case(state)
                BYTE1:out_bytes[23:16] <= in;
                BYTE2:out_bytes[15:8] <= in;
                BYTE3:out_bytes[7:0] <= in;
                DONE:out_bytes[23:16] <= in;
            endcase
        end
    end
endmodule

Fsm serial

又是一道正確率很低的題目，

一開始寫的count==8，一直出錯，要注意count=0也有一個周期的長度，

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
    parameter IDLE=0,START=1,DATA=https://www.cnblogs.com/magnolia666/archive/2022/11/06/2,STOP=3;
    reg[1:0]state,next_state;
    reg[3:0]count;
    
    always@(posedge clk)
    begin
        if(reset)
            state <= IDLE;
        else
            state <= next_state;
    end
    
    always@(posedge clk)
    begin
        if(reset)
            count <= 'd0;
        else if(state == DATA)
            count <= (count>7)?count:count+1'b1;
        else
            count <= 'd0;
    end
    
    always@(*)
    begin
        case(state)
            IDLE:next_state=in?IDLE:START;
            START:next_state=DATA;
            DATA:begin
                if(count==7&&in)
                    next_state=STOP;
                else if(count>7&&in)
                    next_state=IDLE;
                else
                    next_state=DATA;
            end
            STOP:next_state=in?IDLE:START;
        endcase
    end
    assign done=(state==STOP);

endmodule

Fsm serialdata

使用state計數的話整體的資料采集會落后一個周期，所以這題的計數使用next_state來進行判斷，所以上一題的7要改成8，

原理參考三段式狀態機使用case(next_state)用作輸出，否則使用case(state)輸出會落后兩個周期，

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output reg[7:0] out_byte,
    output done
); //

    // Use FSM from Fsm_serial
    parameter IDLE=0,START=1,DATA=https://www.cnblogs.com/magnolia666/archive/2022/11/06/2,STOP=3;
    reg[1:0]state,next_state;
    reg[3:0]count;
    
    always@(posedge clk)
    begin
        if(reset)
            state <= IDLE;
        else
            state <= next_state;
    end
    
    always@(posedge clk)
    begin
        if(reset)
            count <= 'd0;
        else if(next_state == DATA)begin
            out_byte <= {in,out_byte[7:1]};
            count <= (count>8)?count:count+1'b1;
        end
        else
            count <= 'd0;
    end
    
    always@(*)
    begin
        case(state)
            IDLE:next_state=in?IDLE:START;
            START:next_state=DATA;
            DATA:begin
                if(count==8&&in)
                    next_state=STOP;
                else if(count>8&&in)
                    next_state=IDLE;
                else
                    next_state=DATA;
            end
            STOP:next_state=in?IDLE:START;
        endcase
    end
    assign done=(state==STOP);
    // New: Datapath to latch input bits.

endmodule

Fsm serialdp

在上一題的基礎上實作一個奇校驗：通過加入一個冗余位，使得9位資料中的1的個數始終為奇數，

題目給了一個T觸發器，即輸入為1時，輸出翻轉的觸發器，T觸發一般使用一個JK觸發器構成，

debug不能看全部信號的波形也太折磨了，最好還是用vivado仿真調一下，

在經過六次失敗之后，終于成功了，錯誤的原因是T觸發器的in信號經過了選通，導致可能少計了一個周期，其實reset位置合適，in可以直接連接到T觸發器上，

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //

    // Use FSM from Fsm_serial
    parameter IDLE=0,START=1,DATA=https://www.cnblogs.com/magnolia666/archive/2022/11/06/2,STOP=3;
    reg[1:0]state,next_state;
    reg[3:0]count;
    wire odd;
    reg[8:0]data;
    wire parity_reset;

    always@(posedge clk)
    begin
        if(reset)
            state <= IDLE;
        else
            state <= next_state;
    end
    
    always@(posedge clk)
    begin
        if(reset)
            count <= 'd0;
        else if(next_state == DATA)begin
            data <= {in,data[8:1]};
            count <= (count>9)?count:count+1'b1;
        end
        else if(next_state == START)
            count <= 'd0;
    end
    
    always@(*)
    begin
        case(state)
            IDLE:next_state=in?IDLE:START;
            START:next_state=DATA;
            DATA:begin
                if(count==9&&in&&odd)
                    next_state=STOP;
                else if(count>=9&&in)
                    next_state=IDLE;
                else
                    next_state=DATA;
            end
            STOP:next_state=in?IDLE:START;
        endcase
    end
    assign done=(state==STOP);
    // New: Datapath to latch input bits.
    // New: Add parity checking.
    parity u0(clk,parity_reset,in,odd);
    assign out_byte=data[7:0];
    assign parity_reset = reset||next_state ==IDLE||next_state == START;
endmodule

Fsm hdlc

序列檢測器，這里有三個序列需要檢測

0111110: Signal a bit needs to be discarded (disc).
01111110: Flag the beginning/end of a frame (flag).
01111111...: Error (7 or more 1s) (err).

根據題目意思可以構建一個Moore狀態機，結果發現和前面Fsm onehot中的狀態機是一樣的，這不是巧了嗎，前面用的是獨熱碼并且已經寫出了狀態轉移方程，這里直接用就好了，

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
    reg[9:0]state;
    wire[9:0]next_state;
    parameter NONE=10'd0000_0000_01;
    parameter ONE=10'd0000_0000_10;
    parameter TWO=10'd0000_0001_00;
    parameter THREE=10'd0000_0010_00;
    parameter FOUR=10'd0000_0100_00;
    parameter FIVE=10'd0000_1000_00;
    parameter SIX=10'd0001_0000_00;
    parameter ERROR=10'd0010_0000_00;
    parameter DISCARD=10'd0100_0000_00;
    parameter FLAG=10'd1000_0000_00;
    
    always@(posedge clk)
    begin
        if(reset)
            state <= NONE;
        else
            state <= next_state;
    end
    
    assign next_state[0]=~in&&(state[4:0]||state[9:7]);
    assign next_state[1]=in&&(state[0]||state[9:8]);
    assign next_state[2]=in&&state[1];
    assign next_state[3]=in&&state[2];
    assign next_state[4]=in&&state[3];
    assign next_state[5]=in&&state[4];
    assign next_state[6]=in&&state[5];
    assign next_state[7]=in&&state[7:6];
    assign next_state[8]=~in&&state[5];
    assign next_state[9]=~in&&state[6];
    
    assign err=state[7];
    assign disc=state[8];    
    assign flag=state[9]; 

endmodule

有狀態轉換邏輯就是好寫，

Exams/ece241 2013 q8

使用Mealy狀態機，也就是輸出和狀態和輸入都有關，這里使用Moore狀態機會多一個狀態.，而題目要求使用三個狀態，所以最好使用Mealy狀態機，

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
    
    reg[1:0]state,next_state;
    parameter S0=0,S1=1,S2=2;
    
    always@(posedge clk or negedge aresetn)
    begin
        if(~aresetn)
            state <= S0;
        else
            state <= next_state;
    end

    always@(*)
    begin
        case(state)
            S0:next_state=x?S1:S0;
            S1:next_state=x?S1:S2;
            S2:next_state=x?S1:S0;
            default:next_state=S0;
        endcase
    end
    
    assign z=(state==S2)&&x;
        
endmodule

這里使用的是兩段式，輸出直接使用組合邏輯，我一開始寫的三段式，輸出用的時序邏輯，輸入會同時改變次態和輸出，所以電路綜合出來顯示一直是0，暈，

下面是代碼，用來當反面教材，

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output reg z ); 
    
    reg[1:0]state,next_state;
    parameter S0=0,S1=1,S2=2;
    
    always@(posedge clk or negedge aresetn)
    begin
        if(~aresetn)
            state <= S0;
        else
            state <= next_state;
    end

    always@(*)
    begin
        case(state)
            S0:next_state=x?S1:S0;
            S1:next_state=x?S1:S2;
            S2:next_state=x?S1:S0;
            default:next_state=S0;
        endcase
    end
    
    always@(posedge clk or negedge aresetn)
    begin
        if(~aresetn)
            z <= 1'b0;
        else begin
            case(next_state)
                S0:z <= 1'b0;
                S1:z <= 1'b0;
                S2:z <= x;
                default:z <= 1'b0;
            endcase
        end
    end
        
endmodule

Exams/ece241 2014 q5a

這道題一開始沒看懂啥意思，看了一下Rong曄大佬的視頻才懂，

大概意思就是遇到第一個1時開始進行取反運算，由于1000的補碼仍然是1000，所以第一個1保持不變，后面出現的高位全部取反，

注意這里只需要對輸入進行補碼運算，不需要也沒有辦法判斷輸入的數到底是正數還是負數（一開始就是沒想清楚這一點），所以無腦對輸入進行計算就可以了，

這里用S1代表需要輸出1，S2代表需要輸出0，

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    reg [1:0] state,next_state;
    parameter S0=0,S1=1,S2=2;
    
    always@(posedge clk or posedge areset)
    begin
        if(areset)
            state <= S0;
        else 
            state <= next_state;
    end
    
    always@(*)
    begin
        case(state)
            S0:next_state=x?S1:S0;
            S1:next_state=x?S2:S1;
            S2:next_state=x?S2:S1;
        endcase
    end
                
    assign z=(state == S1);
    
endmodule

Exams/ece241 2014 q5b

和上一題是一樣的，注意Moore狀態機比Mealy狀態機多一個狀態，并且Mealy狀態機直接使用組合邏輯輸出會相比Moore狀態機提前一個周期，

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    reg [1:0]state,next_state;
    parameter S0=2'b01,S1=2'b10;
    
    always@(posedge clk or posedge areset)
    begin
        if(areset)
            state <= S0;
        else 
            state <= next_state;
    end
    
    always@(*)
    begin
        case(state)
            S0:next_state=x?S1:S0;
            S1:next_state=S1;
            default:next_state=S0;
        endcase
    end
                
    assign z=(state[0]&&x)||(state[1]&&~x);
    
endmodule

Exams/2014 q3fsm

這道題正確率只有13%

主要困難的地方在于計數每三個周期里w有多少個1，由于這里計數是連續的，所以w的計數不能簡單的清零，在第一個周期時便可以開始判斷w的值，并決定初始化為0還是1，

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);
    parameter A=0,B=1;
    reg state,next_state;
    reg [1:0]w_count,count;
    
    always@(posedge clk)
    begin
        if(reset)
            state <= A;
        else
            state <= next_state;
    end
    
    always@(*)
    begin
        case(state)
            A:next_state=s?B:A;
            B:next_state=B;
        endcase
    end
    
    always@(posedge clk)
    begin
        if(reset)
            count <= 'd0;
        else begin
            if((state==B)&&count <2)
            begin
                count <= count + 1'b1;
            end
            else begin
                count <= 'd0;
            end
        end
    end
    
    always@(posedge clk)
    begin
        if(reset)
            w_count <= 'd0;
        else if(state ==B) begin
            if(count ==0)
            begin
                if(w)
                    w_count <= 'd1;  
                else 
                    w_count <= 'd0; 
            end
            else if(w)
                w_count <=  w_count +1'b1;
        end
    end    
    
    assign z=(count == 'd0)&&(w_count ==2);

endmodule

Exams/2014 q3bfsm

終于來了一道簡單題，

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input x,
    output z
);
    parameter S0=3'b000;
    parameter S1=3'b001;
    parameter S2=3'b010;
    parameter S3=3'b011;
    parameter S4=3'b100;
    
    reg[2:0]state,next_state;
    
    always@(posedge clk)
    begin
        if(reset)
            state <= S0;
        else
            state <= next_state;
    end
    
    always@(*)
    begin
        case(state)
            S0:next_state=x?S1:S0;
            S1:next_state=x?S4:S1;
            S2:next_state=x?S1:S2;
            S3:next_state=x?S2:S1;
            S4:next_state=x?S4:S3;
            default:next_state=S0;
        endcase
    end
    
    assign z=(state==S3)||(state==S4);

endmodule

Exams/2014 q3c

這道題給的clk沒啥用，

module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);
    parameter S0=3'b000;
    parameter S1=3'b001;
    parameter S2=3'b010;
    parameter S3=3'b011;
    parameter S4=3'b100;
    
    reg[2:0]next_state;
    
    always@(*)
    begin
        case(y)
            S0:next_state=x?S1:S0;
            S1:next_state=x?S4:S1;
            S2:next_state=x?S1:S2;
            S3:next_state=x?S2:S1;
            S4:next_state=x?S4:S3;
            default:next_state=S0;
        endcase
    end
    
    assign z=(y==S3)||(y==S4);    
    assign Y0=next_state[0];

endmodule

Exams/m2014 q6b

這題只要求把Y2邏輯寫出來，Y2只在兩種情況為1，即狀態C和狀態D，把所有會跳轉到這兩種狀態的情況列舉出來即可，

module top_module (
    input [3:1] y,
    input w,
    output Y2);
    parameter A=3'b000;
    parameter B=3'b001;
    parameter C=3'b010;
    parameter D=3'b011;
    parameter E=3'b100; 
    parameter F=3'b101; 
    
    assign Y2=(y==B&&~w)||(y==F&&~w)||
        (y==B&&w)||(y==C&&w)||(y==E&&w)||(y==F&&w);

endmodule

Exams/m2014 q6c

做過的題型，要求使用獨熱碼編碼，

module top_module (
    input [6:1] y,
    input w,
    output Y2,
    output Y4);

    parameter A=6'b000_001;
    parameter B=6'b000_010;
    parameter C=6'b000_100;
    parameter D=6'b001_000;
    parameter E=6'b010_000; 
    parameter F=6'b100_000;
    
    assign Y2=y[1]&&~w;
    assign Y4=(y[2]&&w)||(y[3]&&w)||(y[5]&&w)||(y[6]&&w);
    
endmodule

Exams/m2014 q6

直接接著上一題寫，

module top_module (
    input clk,
    input reset,     // synchronous reset
    input w,
    output z);

    parameter A=6'b000_001;
    parameter B=6'b000_010;
    parameter C=6'b000_100;
    parameter D=6'b001_000;
    parameter E=6'b010_000; 
    parameter F=6'b100_000;
    
    reg [6:1]state,next_state;
    always@(posedge clk)
    begin
        if(reset)
            state <= A;
        else 
            state <= next_state;
    end
    
    assign next_state[1]=(state[1]&&w)||(state[4]&&w);
    assign next_state[2]=state[1]&&~w;
    assign next_state[3]=(state[2]&&~w)||(state[6]&&~w);
    assign next_state[4]=(state[2]&&w)||(state[3]&&w)||(state[5]&&w)||(state[6]&&w); 
    assign next_state[5]=(state[3]&&~w)||(state[5]&&~w);
    assign next_state[6]=state[4]&&~w;
    
    assign z=state[5]||state[6];
    
endmodule

Exams/2012 q2fsm

和上一題是一樣的，只不過按題目要求用了兩個always，

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    input w,
    output z
);

    parameter A=3'b000;
    parameter B=3'b001;
    parameter C=3'b010;
    parameter D=3'b011;
    parameter E=3'b100; 
    parameter F=3'b101; 
    
    reg [6:1]state,next_state;
    always@(posedge clk)
    begin
        if(reset)
            state <= A;
        else 
            state <= next_state;
    end
    
    always@(*)
    begin
        case(state)
            A:next_state=w?B:A;
            B:next_state=w?C:D;
            C:next_state=w?E:D;
            D:next_state=w?F:A;
            E:next_state=w?E:D;
            F:next_state=w?C:D;
            default:next_state=A;
        endcase
    end
    
    assign z=(state==E)||(state==F);
    
endmodule

Exams/2012 q2b

為啥還是這道題，稍微變了一點邏輯，

module top_module (
    input [5:0] y,
    input w,
    output Y1,
    output Y3
);
    
    assign Y1=y[0]&&w;
    assign Y3=(y[1]&&~w)||(y[2]&&~w)||(y[4]&&~w)||(y[5]&&~w); 

endmodule

Exams/2013 q2afsm

這個狀態機是一個仲裁器，不難看出，三個設備具有不同的優先級，B>C>D，根據狀態轉移圖不難得出方程，

一開始寫錯了，因為r1、r2、r3順序搞錯了，暈，

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input [3:1] r,   // request
    output [3:1] g   // grant
); 
    
    parameter A=0,B=1,C=2,D=3;
    reg [1:0]state,next_state;
    
    always@(posedge clk)
    begin
        if(~resetn)
            state <= A;
        else
            state <= next_state;
    end
    
    always@(*)
    begin
        case(state)
            A:begin
                casex(r)
                    3'b000:next_state=A;
                    3'bxx1:next_state=B;
                    3'bx10:next_state=C;
                    3'b100:next_state=D;
                endcase
            end
            B:next_state=r[1]?B:A;
            C:next_state=r[2]?C:A;
            D:next_state=r[3]?D:A;
        endcase
    end
    
    assign g[1]=state==B;
    assign g[2]=state==C;
    assign g[3]=state==D;

endmodule

Exams/2013 q2bfsm

瘋狂加狀態就完事了，主要是要理解題目意思，一步一步寫就行了，

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
    parameter A=0,B=1,C=2,D=3,E=4,F=5,G=6,H=7,I=8;
    reg [3:0]state,next_state;
    
    always@(posedge clk)
    begin
        if(~resetn)
            state <= A;
        else
            state <= next_state;
    end
    
    always@(*)
    begin
        case(state)
            A:next_state=B;
            B:next_state=C;
            C:next_state=x?D:C;
            D:next_state=x?D:E;
            E:next_state=x?F:C;
            
            F:next_state=y?H:G;
            G:next_state=y?H:I;
            H:next_state=H;//g=1
            I:next_state=I;//g=0;
        endcase
    end
    
    assign f=(state==B);
    assign g=(state==F)||(state==G)||(state==H);

endmodule

寫了一個星期終于寫完這一節了，淚目，

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