VL11 4位數值比較器電路
根據題目真值表把情況全部列出來，純體力活，
`timescale 1ns/1ns module comparator_4( input [3:0] A , input [3:0] B , output wire Y2 , //A>B output wire Y1 , //A=B output wire Y0 //A<B ); assign Y2 = (A[3]&~B[3])||((~A[3]^B[3])&&(A[2]&~B[2]))||((~A[3]^B[3])&&(~A[2]^B[2])&&(A[1]&~B[1]))||((~A[3]^B[3])&&(~A[2]^B[2])&&(~A[1]^B[1])&&A[0]&~B[0]); assign Y1 = (~A[3]^B[3])&&(~A[2]^B[2])&&(~A[1]^B[1])&&(~A[0]^B[0]); assign Y0 = (~A[3]&B[3])||((~A[3]^B[3])&&(~A[2]&B[2]))||((~A[3]^B[3])&&(~A[2]^B[2])&&~A[1]&B[1])||((~A[3]^B[3])&&(~A[2]^B[2])&&(~A[1]^B[1])&&(~A[0]&B[0])); endmodule
VL12 4bit超前進位加法器電路
最直接的方法：把題目給的公式直接翻譯成Verilog，
`timescale 1ns/1ns module lca_4( input [3:0] A_in , input [3:0] B_in , input C_1 , output wire CO , output wire [3:0] S ); wire [3:0]G; wire [3:0]P; wire [2:0]C; assign G = A_in & B_in; assign P = A_in ^ B_in; assign S = P ^ {C,C_1}; assign {CO,C} = G | (P&{C,C_1}); endmodule
VL13 優先編碼器電路①
注意I1~I9的順序，
`timescale 1ns/1ns module encoder_0( input [8:0] I_n , output reg [3:0] Y_n ); always@(*) begin casex(I_n) 9'b111_111_111:Y_n=4'b1111; 9'b0xx_xxx_xxx:Y_n=4'b0110; 9'b10x_xxx_xxx:Y_n=4'b0111; 9'b110_xxx_xxx:Y_n=4'b1000; 9'b111_0xx_xxx:Y_n=4'b1001; 9'b111_10x_xxx:Y_n=4'b1010; 9'b111_110_xxx:Y_n=4'b1011; 9'b111_111_0xx:Y_n=4'b1100; 9'b111_111_10x:Y_n=4'b1101; 9'b111_111_110:Y_n=4'b1110; default:Y_n=0; endcase end endmodule
VL14 用優先編碼器①實作鍵盤編碼電路
將9-4編碼器拓展成10-4編碼器，因為高位優先級更高，所以高9位直接輸入優先編碼器，最低位等于0且其余位全部為1時，輸出為0，
`timescale 1ns/1ns module encoder_0( input [8:0] I_n , output reg [3:0] Y_n ); always @(*)begin casex(I_n) 9'b111111111 : Y_n = 4'b1111; 9'b0xxxxxxxx : Y_n = 4'b0110; 9'b10xxxxxxx : Y_n = 4'b0111; 9'b110xxxxxx : Y_n = 4'b1000; 9'b1110xxxxx : Y_n = 4'b1001; 9'b11110xxxx : Y_n = 4'b1010; 9'b111110xxx : Y_n = 4'b1011; 9'b1111110xx : Y_n = 4'b1100; 9'b11111110x : Y_n = 4'b1101; 9'b111111110 : Y_n = 4'b1110; default : Y_n = 4'b1111; endcase end endmodule module key_encoder( input [9:0] S_n , output wire[3:0] L , output wire GS ); wire [3:0]Y; encoder_0 u0( .I_n(S_n[9:1]), .Y_n(Y) ); assign GS = !(Y==4'b1111&&S_n[0]); assign L = (~S_n[0]&&Y==4'b1111)?0:~Y; endmodule
VL15 優先編碼器Ⅰ
也是純體力活，，，
`timescale 1ns/1ns module encoder_83( input [7:0] I , input EI , output wire [2:0] Y , output wire GS , output wire EO ); assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]); assign Y[1] = EI & (I[7] | I[6] | (~I[7]&~I[6]&~I[5]&~I[4]&I[3])|(~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&I[2])); assign Y[0] = EI & (I[7] |(~I[7]&~I[6]&I[5])|(~I[7]&~I[6]&~I[5]&~I[4]&I[3])|(~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&I[1])); assign GS = ~((~EI)|(I==0)); assign EO = (I==0); endmodule
VL16 使用8線-3線優先編碼器Ⅰ實作16線-4線優先編碼器
這題有點意思，數電里其實學過，但是有點不太記得了，
分析可知：高位優先級更高，所以當高位有效時，低位肯定是全0，所以此時需要關斷低位使能，也就是把高位編碼器的EO接到低位編碼器的EI，
不難看出GS代表編碼器正常作業，所以可以把兩個編碼器的GS相或輸出，
高位正常作業時，最高位為1，與此編碼器輸出一致，所以可以把高位編碼器的GS作為最高位，
低位時兩個編碼器輸出相或，因為兩個都是8位編碼器，高八位有效時也只是最高位為1，其他位行為與低位一致，
`timescale 1ns/1ns module encoder_83( input [7:0] I , input EI , output wire [2:0] Y , output wire GS , output wire EO ); assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]); assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]); assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]); assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0]; assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]); //assign GS = EI&(| I); endmodule module encoder_164( input [15:0] A , input EI , output wire [3:0] L , output wire GS , output wire EO ); wire E; wire GS0,GS1; wire [2:0]Y0,Y1; encoder_83 u0( .I(A[15:8]), .EI(EI), .Y(Y0), .GS(GS0), .EO(E) ); encoder_83 u1( .I(A[7:0]), .EI(E), .Y(Y1), .GS(GS1), .EO(EO) ); assign L={GS0,Y0|Y1}; assign GS=GS1|GS0; endmodule
VL17 用3-8譯碼器實作全減器
這題不難，只需要通過3-8譯碼器便可以實作任何三輸入的組合邏輯，
`timescale 1ns/1ns module decoder_38( input E , input A0 , input A1 , input A2 , output reg Y0n , output reg Y1n , output reg Y2n , output reg Y3n , output reg Y4n , output reg Y5n , output reg Y6n , output reg Y7n ); always @(*)begin if(!E)begin Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; end else begin case({A2,A1,A0}) 3'b000 : begin Y0n = 1'b0; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; end 3'b001 : begin Y0n = 1'b1; Y1n = 1'b0; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; end 3'b010 : begin Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b0; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; end 3'b011 : begin Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b0; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; end 3'b100 : begin Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b0; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; end 3'b101 : begin Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b0; Y6n = 1'b1; Y7n = 1'b1; end 3'b110 : begin Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b0; Y7n = 1'b1; end 3'b111 : begin Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b0; end default: begin Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; end endcase end end endmodule module decoder1( input A , input B , input Ci , output wire D , output wire Co ); wire Y0n,Y1n,Y2n,Y3n,Y4n,Y5n,Y6n,Y7n; decoder_38 u0( .E(1), .A0(Ci), .A1(B), .A2(A), .Y0n(Y0n), .Y1n(Y1n), .Y2n(Y2n), .Y3n(Y3n), .Y4n(Y4n), .Y5n(Y5n), .Y6n(Y6n), .Y7n(Y7n) ); assign D = ~Y4n||~Y7n||~Y1n||~Y2n; assign Co = ~Y1n||~Y2n||~Y3n||~Y7n; endmodule
VL18 實作3-8譯碼器①
`timescale 1ns/1ns module decoder_38( input E1_n , input E2_n , input E3 , input A0 , input A1 , input A2 , output wire Y0_n , output wire Y1_n , output wire Y2_n , output wire Y3_n , output wire Y4_n , output wire Y5_n , output wire Y6_n , output wire Y7_n ); assign Y0_n = (~E3||E2_n||E1_n)?1:~(~A2&&~A1&&~A0); assign Y1_n = (~E3||E2_n||E1_n)?1:~(~A2&&~A1&&A0); assign Y2_n = (~E3||E2_n||E1_n)?1:~(~A2&&A1&&~A0); assign Y3_n = (~E3||E2_n||E1_n)?1:~(~A2&&A1&&A0); assign Y4_n = (~E3||E2_n||E1_n)?1:~(A2&&~A1&&~A0); assign Y5_n = (~E3||E2_n||E1_n)?1:~(A2&&~A1&&A0); assign Y6_n = (~E3||E2_n||E1_n)?1:~(A2&&A1&&~A0); assign Y7_n = (~E3||E2_n||E1_n)?1:~(A2&&A1&&A0); endmodule
VL19 使用3-8譯碼器①實作邏輯函式
和VL17類似，注意高低位，
`timescale 1ns/1ns module decoder_38( input E1_n , input E2_n , input E3 , input A0 , input A1 , input A2 , output wire Y0_n , output wire Y1_n , output wire Y2_n , output wire Y3_n , output wire Y4_n , output wire Y5_n , output wire Y6_n , output wire Y7_n ); wire E ; assign E = E3 & ~E2_n & ~E1_n; assign Y0_n = ~(E & ~A2 & ~A1 & ~A0); assign Y1_n = ~(E & ~A2 & ~A1 & A0); assign Y2_n = ~(E & ~A2 & A1 & ~A0); assign Y3_n = ~(E & ~A2 & A1 & A0); assign Y4_n = ~(E & A2 & ~A1 & ~A0); assign Y5_n = ~(E & A2 & ~A1 & A0); assign Y6_n = ~(E & A2 & A1 & ~A0); assign Y7_n = ~(E & A2 & A1 & A0); endmodule module decoder0( input A , input B , input C , output wire L ); wire Y0_n,Y1_n,Y2_n,Y3_n,Y4_n,Y5_n,Y6_n,Y7_n; decoder_38 u0( .E1_n(0), .E2_n(0), .E3(1), .A0(C), .A1(B), .A2(A), .Y0_n(Y0_n), .Y1_n(Y1_n), .Y2_n(Y2_n), .Y3_n(Y3_n), .Y4_n(Y4_n), .Y5_n(Y5_n), .Y6_n(Y6_n), .Y7_n(Y7_n) ); assign L = (~Y3_n||~Y1_n)||(~Y6_n||~Y7_n); endmodule
VL20 資料選擇器實作邏輯電路
這題可以畫一個卡諾圖，
用AB做資料選擇，C的各種邏輯為要選擇的資料，
同樣注意高低位，
`timescale 1ns/1ns module data_sel( input S0 , input S1 , input D0 , input D1 , input D2 , input D3 , output wire Y ); assign Y = ~S1 & (~S0&D0 | S0&D1) | S1&(~S0&D2 | S0&D3); endmodule module sel_exp( input A , input B , input C , output wire L ); wire S0,S1,D0,D1,D2,D3; data_sel u0( .S0(B) , .S1(A) , .D0(0) , .D1(C) , .D2(~C) , .D3(1) , .Y(L) ); endmodule
轉載請註明出處，本文鏈接：https://www.uj5u.com/houduan/544711.html
標籤：其他
上一篇：springboot01