VL21 根據狀態轉移表實作時序電路
寫一個簡單的Moore狀態機就可以了，太短就懶得寫三段式了，
`timescale 1ns/1ns module seq_circuit( input A , input clk , input rst_n, output wire Y ); reg [1:0]state; always@(posedge clk or negedge rst_n) begin if(~rst_n) state <= 0; else begin case(state) 0:state <= A?3:1; 1:state <= A?0:2; 2:state <= A?1:3; 3:state <= A?2:0; endcase end end assign Y = (state == 2'b11); endmodule
VL22 根據狀態轉移圖實作時序電路
因為輸出定義的是wire變數，這里就直接用的assign輸出了，
`timescale 1ns/1ns module seq_circuit( input C , input clk , input rst_n, output wire Y ); reg [1:0]state; reg [1:0]next_state; always@(posedge clk or negedge rst_n) begin if(~rst_n) state <= 0; else state <= next_state; end always@(*) begin case(state) 0:next_state = C?1:0; 1:next_state = C?1:3; 2:next_state = C?2:0; 3:next_state = C?2:3; endcase end assign Y = (state == 3)||(state == 2&&C); endmodule
VL23 ROM的簡單實作
初始化想用initial的，但是initial不可綜合，因為介面定義的是wire，所以直接用assign輸出，
ram的話就在always塊內賦值即可，
`timescale 1ns/1ns module rom( input clk, input rst_n, input [7:0]addr, output [3:0]data ); reg [3:0]rom[0:7]; always@(posedge clk or negedge rst_n) begin if(~rst_n)begin rom[0] <= 0; rom[1] <= 2; rom[2] <= 4; rom[3] <= 6; rom[4] <= 8; rom[5] <= 10; rom[6] <= 12; rom[7] <= 14; end end assign data =https://www.cnblogs.com/magnolia666/archive/2023/02/23/ rom[addr]; endmodule
VL24 邊沿檢測
這題比較簡單，把輸入打一拍再進行比較，注意時序輸出即可，
`timescale 1ns/1ns module edge_detect( input clk, input rst_n, input a, output reg rise, output reg down ); reg a_reg; always@(posedge clk or negedge rst_n)begin if(~rst_n)begin rise <= 1'b0; down <= 1'b0; a_reg <= 1'b0; end else begin a_reg <= a; if(a&&~a_reg) rise <= 1'b1; else rise <= 1'b0; if(~a&&a_reg) down <= 1'b1; else down <= 1'b0; end end endmodule
基礎題還是比較簡單的，明天開始進階，
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