VL59 根據RTL圖撰寫Verilog程式
這題比較簡單，照著寫就好了，
`timescale 1ns/1ns module RTL( input clk, input rst_n, input data_in, output reg data_out ); reg data_in_reg; always@(posedge clk) begin if(~rst_n) begin data_in_reg <= 1'b0; data_out <= 1'b0; end else begin data_in_reg <= data_in; data_out <= data_in&~data_in_reg; end end endmodule
VL60 使用握手信號實作跨時鐘域資料傳輸
題目只給了一個模塊的介面，實際看testbench要寫兩個模塊，
一開始用狀態機寫的，實在和答案對不上，還是照著題解寫了，單bit資料跨時鐘域常用方法：打兩拍，
`timescale 1ns/1ns module data_driver( input clk_a, input rst_n, input data_ack, output reg [3:0]data, output reg data_req ); reg data_ack_reg_1; reg data_ack_reg_2; always @ (posedge clk_a or negedge rst_n) begin if (!rst_n) begin data_ack_reg_1 <= 1'b0; data_ack_reg_2 <= 1'b0; end else begin data_ack_reg_1 <= data_ack; data_ack_reg_2 <= data_ack_reg_1; end end always@(posedge clk_a or negedge rst_n) begin if(~rst_n) data <= 'd0; else if(~data_ack_reg_2&data_ack_reg_1)//每次傳輸結束資料+1 data <= data + 1'b1; end reg [3:0]count; always@(posedge clk_a or negedge rst_n) begin if(~rst_n) count <= 'd0; else if(~data_req) count <= count + 1; else count <= 0; end always@(posedge clk_a or negedge rst_n) begin if(~rst_n) data_req <= 'd0; else if(count == 4) data_req <= 1'b1; else if(~data_ack_reg_2&data_ack_reg_1)//傳輸結束，data_req清零 data_req <= 1'b0; end endmodule module data_receiver( input clk_b, input rst_n, input [3:0]data, input data_req, output reg data_ack ); reg data_req_reg_1; reg data_req_reg_2; always @ (posedge clk_b or negedge rst_n) begin if (!rst_n) begin data_req_reg_1 <= 0; data_req_reg_2 <= 0; end else begin data_req_reg_1 <= data_req; data_req_reg_2 <= data_req_reg_1; end end always@(posedge clk_b or negedge rst_n) begin if(~rst_n) data_ack <= 1'b0; else if(data_req_reg_2 == 1'b1) data_ack <= 1'b1; else data_ack <= 1'b0; end endmodule
VL61 自動售賣機
感覺用計數器會很簡單，狀態機復雜一點，不過題目要求用狀態機那就用吧，
看了一下，感覺兩個狀態應該就夠了，一個狀態代表售賣機內沒錢，一個狀態代表售賣機內有5元錢，
`timescale 1ns/1ns module sale( input clk , input rst_n , input sel ,//sel=0,5$dranks,sel=1,10&=$drinks input [1:0] din ,//din=1,input 5$,din=2,input 10$ output reg [1:0] drinks_out,//drinks_out=1,output 5$ drinks,drinks_out=2,output 10$ drinks output reg change_out ); reg state,next_state; localparam S0=0,S1=1; always@(posedge clk or negedge rst_n) begin if(~rst_n) state <= S0; else state <= next_state; end always@(*) begin case(state) S0:begin//0 if(sel==0&&din==1||sel==1&&din==2) next_state = S0; else if(sel==1&&din==1) next_state = S1; else next_state = S0; end S1:begin//5 next_state = din?S0:S1; end endcase end always@(posedge clk or negedge rst_n) begin if(~rst_n)begin drinks_out <= 0; change_out <= 0; end else begin case(state) S0:begin if(sel==0&&din==1)begin drinks_out <= 1; change_out <= 0; end else if(sel==1&&din==2)begin drinks_out <= 2; change_out <= 0; end else if(sel==0&&din==2)begin drinks_out <= 1; change_out <= 1; end else begin drinks_out <= 0; change_out <= 0; end end S1:begin if(sel==0&&din==1)begin drinks_out <= 1; change_out <= 1; end else if(sel==1&&din==2)begin drinks_out <= 2; change_out <= 1; end else if(sel==1&&din==1)begin drinks_out <= 2; change_out <= 0; end else begin drinks_out <= 0; change_out <= 0; end end endcase end end endmodule
VL62 序列發生器
直接移位暫存器秒了，不過用狀態機的話所用暫存器會少一點，
`timescale 1ns/1ns module sequence_generator( input clk, input rst_n, output reg data ); reg [5:0]data_reg; always@(posedge clk or negedge rst_n) begin if(~rst_n)begin data_reg <= 6'b001011; data <= 1'b0; end else begin data_reg <= {data_reg[4:0],data_reg[5]}; data <= data_reg[5]; end end endmodule
VL63 并串轉換
說是華為暑期實習的題，感覺題目出的一般，不懂是要考啥，
`timescale 1ns/1ns module huawei5( input wire clk , input wire rst , input wire [3:0]d , output wire valid_in , output wire dout ); //*************code***********// reg [3:0]data; reg valid; reg [1:0]count; always@(posedge clk or negedge rst) begin if(!rst)begin data <= 'd0; valid <= 1'b0; count <= 'd0; end else begin if(count == 'd3)begin valid <= 1'b1; count <= 0; data <= d; end else begin valid <= 1'b0; count <= count + 1; data <= data << 1; end end end assign dout = data[3]; assign valid_in = valid; //*************code***********// endmodule
VL64 時鐘切換
核心是沒有毛刺，我以為把sel打兩拍用來控制就行了，結果發現想簡單了，參考（數字 IC 設計）5.4 時鐘切換 - 知乎 (zhihu.com)
為了防止兩個輸出產生毛刺，兩個時鐘不能進行相反的極性轉換，由圖中clk0和clk1可以看出clk0的上升沿和clk1的下降沿是重合的，為避免毛刺的產生，需要在兩個時鐘都為低電平的時候進行時鐘切換，
反饋信號q1
`timescale 1ns/1ns module huawei6( input wire clk0 , input wire clk1 , input wire rst , input wire sel , output wire clk_out ); //*************code***********// reg q0, q1; always@(negedge clk0 or negedge rst) if(!rst) q0 <= 0; else q0 <= ~sel & ~q1; always@(negedge clk1 or negedge rst) if(!rst) q1 <= 0; else q1 <= sel & ~q0; assign clk_out = (q0 & clk0) | (q1 & clk1); //*************code***********// endmodule
VL65 狀態機與時鐘分頻
也可以用四個狀態，更簡單一點，
`timescale 1ns/1ns module huawei7( input wire clk , input wire rst , output reg clk_out ); //*************code***********// reg[1:0]count; reg state,next_state; localparam S0=0,S1=1; always@(posedge clk or negedge rst) begin if(!rst) state <= S0; else state <= next_state; end always@(*) begin case(state) S0:next_state=S1; S1:next_state=(count==2)?S0:S1; endcase end always@(posedge clk or negedge rst) begin if(!rst) clk_out <= 1'b0; else begin if(state==S0) clk_out <= 1'b1; else clk_out <= 1'b0; end end always@(posedge clk or negedge rst) begin if(!rst) clk_out <= 1'b0; else begin if(state==S1) count <= count + 1; else count <= 0; end end //*************code***********// endmodule
VL66 超前進位加法器
超前進位加法器原理：
注意！進位C必須要拆開劃成最后那個運算式，不然Cn+1需要Cn的值的話，仍然會導致組合邏輯越來越長，劃成最后的運算式，Ci始終是三級組合邏輯：1、P、G的運算 2、多輸入與門 3、或門，
`timescale 1ns/1ns module huawei8//四位超前進位加法器 ( input wire [3:0]A, input wire [3:0]B, output wire [4:0]OUT ); //*************code***********// wire [3:0] G; wire [3:0] P; wire [3:0] F; wire [4:1] C; Add1 u0 ( .a(A[0]), .b(B[0]), .C_in(1'b0), .f(F[0]), .g(G[0]), .p(P[0]) ); Add1 u1 ( .a(A[1]), .b(B[1]), .C_in(C[1]), .f(F[1]), .g(G[1]), .p(P[1]) ); Add1 u2 ( .a(A[2]), .b(B[2]), .C_in(C[2]), .f(F[2]), .g(G[2]), .p(P[2]) ); Add1 u3 ( .a(A[3]), .b(B[3]), .C_in(C[3]), .f(F[3]), .g(G[3]), .p(P[3]) ); CLA_4 u4 ( .P(P), .G(G), .C_in(C_in), .Ci(C), .Gm(), .Pm() ); assign OUT={C[4],F}; //*************code***********// endmodule //////////////下面是兩個子模塊//////// module Add1 ( input a, input b, input C_in, output f, output g, output p ); assign f = a^b^C_in;//每一位的輸出 assign g = a&b;//生成信號 assign p = a|b;//傳播信號 endmodule //CLA Carry Look Ahead module CLA_4( input [3:0]P, input [3:0]G, input C_in, output [4:1]Ci, output Gm, output Pm ); assign Ci[1]=G[0]|P[0]&C_in; assign Ci[2]=G[1]|P[1]&G[0]|P[1]&P[0]&C_in; assign Ci[3]=G[2]|P[2]&G[1]|P[2]&P[1]&G[0]|P[2]&P[1]&P[0]&C_in; assign Ci[4]=G[3]|P[3]&G[2]|P[3]&P[2]&G[1]|P[3]&P[2]&P[1]&G[0]|P[3]&P[2]&P[1]&P[0]&C_in; //注意這里一定要拆開寫，不然就和行波進位加法器差不多了， //Gm和Pm是用來拓展更高位加法器的， assign Gm=G[3]|P[3]&G[2]|P[3]&P[2]&G[1]|P[3]&P[2]&P[1]&G[0]; assign Pm=P[3]&P[2]&P[1]&P[0]; endmodule
VL67 十六進制計數器
這題放這里多少有點離譜，，
`timescale 1ns/1ns module counter_16( input clk , input rst_n , output reg [3:0] Q ); always @(posedge clk or negedge rst_n) begin if (!rst_n) begin Q <= 4'b0; end else begin Q <= Q +1'b1; end end endmodule
VL68 同步FIFO
之前寫過，注意按題目給的介面，reg輸出wfull和rempty會晚一個周期，實際要么在下一個讀/寫要空/滿的時候通過reg輸出，或者組合邏輯輸出，
`timescale 1ns/1ns /**********************************RAM************************************/ module dual_port_RAM #(parameter DEPTH = 16, parameter WIDTH = 8)( input wclk ,input wenc ,input [$clog2(DEPTH)-1:0] waddr ,input [WIDTH-1:0] wdata ,input rclk ,input renc ,input [$clog2(DEPTH)-1:0] raddr ,output reg [WIDTH-1:0] rdata ); reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1]; always @(posedge wclk) begin if(wenc) RAM_MEM[waddr] <= wdata; end always @(posedge rclk) begin if(renc) rdata <= RAM_MEM[raddr]; end endmodule /**********************************SFIFO************************************/ module sfifo#( parameter WIDTH = 8, parameter DEPTH = 16 )( input clk , input rst_n , input winc , input rinc , input [WIDTH-1:0] wdata , output reg wfull , output reg rempty , output wire [WIDTH-1:0] rdata ); parameter ADDR_WIDTH = $clog2(DEPTH); reg [ADDR_WIDTH:0]waddr,raddr;//多一位用于比較空滿 always@(posedge clk or negedge rst_n) begin if(~rst_n) waddr <= 'd0; else if(winc&&~wfull) waddr <= waddr + 1; end always@(posedge clk or negedge rst_n) begin if(~rst_n) raddr <= 'd0; else if(rinc&&~rempty) raddr <= raddr + 1; end /*空滿判斷*/ always@(posedge clk or negedge rst_n) begin if(~rst_n)begin wfull <= 'd0; rempty <= 'd0; end else begin wfull <= (waddr[ADDR_WIDTH]==~raddr[ADDR_WIDTH])&&(waddr[ADDR_WIDTH-1:0]==raddr[ADDR_WIDTH-1:0]); rempty <= (raddr==waddr); end end dual_port_RAM #(.WIDTH(WIDTH),.DEPTH(DEPTH)) U0( .wclk(clk), .wenc(winc&&~wfull), .waddr(waddr[ADDR_WIDTH-1:0]), .wdata(wdata), .rclk(clk), .renc(rinc&&~rempty), .raddr(raddr[ADDR_WIDTH-1:0]), .rdata(rdata) ); endmodule
VL69 脈沖同步器（快到慢）
又是在前面做過的題，【牛客】6 跨時鐘域傳輸 - Magnolia666 - 博客園 (cnblogs.com)
sig_a在時鐘域a持續一個周期，在這個周期翻轉toggle電平，下一個脈沖再恢復toggle低電平，把toggle信號在時鐘域b打兩拍，再恢復成單周期脈沖，
`timescale 100ps/100ps module pulse_detect( input clka , input clkb , input rst_n , input sig_a , output sig_b ); reg toggle; always@(posedge clka or negedge rst_n) begin if(!rst_n) toggle <= 1'b0; else toggle <= sig_a?~toggle:toggle; end reg [2:0]sig_syn; always@(posedge clkb or negedge rst_n) begin if(!rst_n) sig_syn <= 'd0; else begin sig_syn <= {sig_syn[1:0],toggle}; end end assign sig_b = sig_syn[2]^sig_syn[1]; endmodule
VL70 序列檢測器（Moore型）
要求使用Moore狀態機，也就是輸出只和狀態有關，注意是不重疊檢測，
`timescale 1ns/1ns module det_moore( input clk , input rst_n , input din , output reg Y ); reg[2:0]state,next_state; localparam S0=0,S1=1,S2=2,S3=3,S4=4; always@(posedge clk or negedge rst_n) begin if(!rst_n) state <= S0; else state <= next_state; end always@(*) begin case(state) S0:next_state = din?S1:S0; S1:next_state = din?S2:S0; S2:next_state = din?S2:S3; S3:next_state = din?S4:S0; S4:next_state = din?S1:S0; endcase end always@(posedge clk or negedge rst_n) begin if(!rst_n) Y <= 1'b0; else begin if(state == S4) Y <= 1'b1; else Y <= 1'b0; end end endmodule
VL71 乘法與位運算
要求資源最少，那肯定是移位資源少了，
`timescale 1ns/1ns module dajiang13( input [7:0] A, output [15:0] B ); //*************code***********// assign B = (A<<8)-(A<<2)-A; //*************code***********// endmodule
VL72 全加器
要求使用半加器實作全加器，半加器沒有低位的進位，全加器有，
我寫的：
`timescale 1ns/1ns module add_half( input A , input B , output wire S , output wire C ); assign S = A ^ B; assign C = A & B; endmodule /***************************************************************/ module add_full( input A , input B , input Ci , output wire S , output wire Co ); wire S_half,C_half; assign S = S_half^Ci; assign Co = C_half | (A&Ci) |(B&Ci); add_half u0( .A(A), .B(B), .S(S_half), .C(C_half) ); endmodule
看了一下答案，其實可以用兩個半加器實作全加器:
`timescale 1ns/1ns module add_half( input A , input B , output wire S , output wire C ); assign S = A ^ B; assign C = A & B; endmodule /***************************************************************/ module add_full( input A , input B , input Ci , output wire S , output wire Co ); wire S1,Co1,Co2; add_half u0( .A(A), .B(B), .S(S1), .C(Co1) ); add_half u1( .A(Ci), .B(S1), .S(S), .C(Co2) ); assign Co = Co1|Co2; endmodule
確實這樣寫才更合理些，
VL73 串行進位加法器
或者叫行波進位加法器，加法器級聯即可，
`timescale 1ns/1ns module add_4( input [3:0] A , input [3:0] B , input Ci , output wire [3:0] S , output wire Co ); wire [3:1]C; add_full u0( .A(A[0]), .B(B[0]), .Ci(Ci), .S(S[0]), .Co(C[1]) ); add_full u1( .A(A[1]), .B(B[1]), .Ci(C[1]), .S(S[1]), .Co(C[2]) ); add_full u2( .A(A[2]), .B(B[2]), .Ci(C[2]), .S(S[2]), .Co(C[3]) ); add_full u3( .A(A[3]), .B(B[3]), .Ci(C[3]), .S(S[3]), .Co(Co) ); endmodule
VL74 異步復位同步釋放
對復位信號做兩級同步，消除亞穩態，具體可以參考【《硬體架構的藝術》讀書筆記】02 時鐘和復位（3） - Magnolia666 - 博客園 (cnblogs.com)
`timescale 1ns/1ns module ali16( input clk, input rst_n, input d, output reg dout ); //*************code***********// reg [1:0]rst_n_syn; always@(posedge clk or negedge rst_n) begin if(~rst_n) rst_n_syn <= 2'b0; else rst_n_syn <= {rst_n_syn[0],1'b1}; end always@(posedge clk or negedge rst_n_syn[1]) begin if(~rst_n_syn[1]) dout <= 1'b0; else dout <= d; end //*************code***********// endmodule
VL75 求最小公倍數
查了一下，求最大公約數用的輾轉相除法，又想起了高中被數論支配的恐懼，
原理：兩個數的最大公約數等于它們中較小的數和兩數之差的最大公約數，
求最小公倍數則根據最小公倍數等于兩數之積除以他們的最大公約數，可以直接用一個'/'表示，
不過這里標答寫的兩段式代碼感覺有點奇怪，每次狀態跳變都會多延一個周期，下面我修改之后的代碼，
`timescale 1ns/1ns module lcm#( parameter DATA_W = 8) ( input [DATA_W-1:0] A, input [DATA_W-1:0] B, input vld_in, input rst_n, input clk, output wire [DATA_W*2-1:0] lcm_out, output wire [DATA_W-1:0] mcd_out, output reg vld_out ); reg [DATA_W*2-1:0] mcd,a_buf,b_buf; reg [DATA_W*2-1:0] mul_buf; reg [1:0] cur_st,nxt_st; parameter IDLE= 2'b00,S0 = 2'b01, S1 = 2'b10; always @(posedge clk or negedge rst_n) if (!rst_n) cur_st <= IDLE; else cur_st <= nxt_st; always@(*) begin case(cur_st) IDLE:nxt_st = vld_in?S0:IDLE; S0:nxt_st = (a_buf==b_buf)?S1:S0; S1:nxt_st = IDLE; default:nxt_st = IDLE; endcase end always @(posedge clk or negedge rst_n) begin if (!rst_n) begin mcd <= 0; a_buf <= 0; b_buf <= 0; mul_buf <= 0; vld_out <= 1'b0; end else begin case (cur_st) IDLE:if(vld_in) begin a_buf <= A; b_buf <= B; mul_buf <= A*B; vld_out <= 1'b0; end else vld_out <= 1'b0; S0:if(a_buf!=b_buf)begin if(a_buf>b_buf) a_buf <= a_buf - b_buf; else b_buf <= b_buf - a_buf; end S1:begin mcd <= b_buf; vld_out <= 1'b1; end endcase end end assign mcd_out = mcd; assign lcm_out = mul_buf/mcd; endmodule
VL76 任意奇數倍時鐘分頻
也是之前寫過的，用一個上升沿計數器和一個下降沿計數器即可，
為了滿足題目波形，強行把下降沿時鐘提前一個周期翻轉了，
`timescale 1ns/1ns module clk_divider #(parameter dividor = 5) ( input clk_in, input rst_n, output clk_out ); reg clk_pos,clk_neg; reg [3:0]cnt0,cnt1; always@(posedge clk_in or negedge rst_n) begin if(~rst_n)begin clk_pos <= 1'b0; cnt0 <= 'd0; end else begin cnt0 <= (cnt0 <dividor-1)?cnt0+1:0; if(cnt0==dividor-1||cnt0==(dividor-1)/2) clk_pos <= ~clk_pos; end end always@(negedge clk_in or negedge rst_n) begin if(~rst_n)begin clk_neg <= 1'b0; cnt1 <= 'd0; end else begin cnt1 <= (cnt1 <dividor-1)?cnt1+1:0; if(cnt1==dividor-2||cnt1==(dividor-1)/2-1) clk_neg <= ~clk_neg; end end assign clk_out = clk_pos|clk_neg; endmodule
VL77 撰寫乘法器求解演算法運算式
主要就是要寫一個4bit乘法器，用移位實作即可；
感覺自己代碼沒錯，不知道為啥牛客一直出錯
`timescale 1ns/1ns module calculation( input clk, input rst_n, input [3:0] a, input [3:0] b, output [8:0] c ); wire [8:0]c1,c2; mult4 u0( .clk(clk), .rst_n(rst_n), .a(12), .b(a), .c(c1) ); mult4 u1( .clk(clk), .rst_n(rst_n), .a(5), .b(b), .c(c2) ); assign c = c1+c2; endmodule module mult4( input clk, input rst_n, input [3:0] a, input [3:0] b, output reg[8:0] c ); wire [8:0]c_temp[3:0]; genvar i; generate for(i=0;i<4;i=i+1) assign c_temp[i] = a[i]?b<<i:0; endgenerate always@(posedge clk or negedge rst_n) begin if(!rst_n) c <= 'd0; else begin c <= c_temp[0] + c_temp[1] + c_temp[2] + c_temp[3]; end end endmodule
總算是刷完了，刷這個還是浪費了很多時間的，題目質量一般，而且還經常出錯，接下來要好好準備實習了，
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