求助大佬錯誤怎么改：Warning (10230): Verilog HDL assignment warning at Count_4bit.v(44): truncated value with size 32 to match size of target (4)
Error (10028): Can't resolve multiple constant drivers for net "Q[3]" at Count_4bit.v(28)
Error (10029): Constant driver at Count_4bit.v(7)
Error (10028): Can't resolve multiple constant drivers for net "Q[2]" at Count_4bit.v(28)
Error (10028): Can't resolve multiple constant drivers for net "Q[1]" at Count_4bit.v(28)
Error (10028): Can't resolve multiple constant drivers for net "Q[0]" at Count_4bit.v(28)
Error (10028): Can't resolve multiple constant drivers for net "Cy" at Count_4bit.v(28)
Error (12153): Can't elaborate top-level user hierarchy
Info (144001): Generated suppressed messages file D:/exp4_count/output_files/Count_4bit.map.smsg
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 7 errors, 2 warnings
Error: Peak virtual memory: 4585 megabytes
Error: Processing ended: Mon Nov 04 22:23:58 2019
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:00
Error (293001): Quartus II Full Compilation was unsuccessful. 9 errors, 2 warnings
module Count_4bit(clk,EN,Q,nCR,Cy,a,b,c,d,e,f,g,h);
input clk,EN,nCR;
output [3:0]Q;
output Cy,a,b,c,d,e,f,g,h;
reg [3:0]Q;
reg Cy,a,b,c,d,e,f,g,h;
always@(posedge clk)
begin
if(~nCR)
begin
Q<=0;
Cy<=0;
end
else if(EN)
begin
if(Q==49999999)
begin
Q<=0;
Cy=1;
end
else
begin
Q<=Q+1;
Cy=0;
end
end
end
always@(posedge clk)
begin
if(~nCR)
begin
Q<=0;
Cy<=0;
end
else if(EN)
begin
if(Q==9)
begin
Q<=0;
Cy=1;
end
else
begin
Q<=Q+1;
Cy=0;
end
end
end
always@({Q})
begin
case({Q})
4'd0:{h,g,f,e,d,c,b,a}=8'b1100_0000;
4'd1:{h,g,f,e,d,c,b,a}=8'b1111_1001;
4'd2:{h,g,f,e,d,c,b,a}=8'b1010_0100;
4'd3:{h,g,f,e,d,c,b,a}=8'b1011_0000;
4'd4:{h,g,f,e,d,c,b,a}=8'b1001_1001;
4'd5:{h,g,f,e,d,c,b,a}=8'b1001_0010;
4'd6:{h,g,f,e,d,c,b,a}=8'b1000_0010;
4'd7:{h,g,f,e,d,c,b,a}=8'b1111_1000;
4'd8:{h,g,f,e,d,c,b,a}=8'b1000_0000;
4'd9:{h,g,f,e,d,c,b,a}=8'b1001_0000;
default:{h,g,f,e,d,c,b,a}=8'b1111_1111;
endcase
end
endmodule
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