我的一個誤差產生模塊代碼如下
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity yuan_error_gen IS
PORT(en,clk,rst:IN STD_LOGIC;
rk,yk:IN SIGNED(7 DOWNTO 0);
ek,ek_1,ek_2,ek_acc:OUT SIGNED(7 DOWNTO 0));
end entity yuan_error_gen;
architecture behavior of yuan_error_gen is
signal temp1:std_logic ;
signal temp2:std_logic ;
signal ek1,ek1_1,ek1_2,ek1_acc:SIGNED(7 DOWNTO 0);
begin
ek <= ek1;
ek_1 <= ek1_1;
ek_2 <= ek1_2;
ek_acc <= ek1_acc;
PROCESS(en,temp2)
BEGIN
IF(en'EVENT AND en='1') THEN
temp1 <= '1';
IF(temp2 ='0')THEN
temp1 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS(clk,temp1,rst)
BEGIN
IF(clk'EVENT AND clk='1') THEN
IF(rst='1')THEN
temp2 <= '1';
ek1 <= "00000000";
ek1_1 <= "00000000";
ek1_2 <= "00000000";
ek1_acc <= "00000000";
ELSIF(temp1 ='1')THEN
temp2 <= '1';
ek1 <= rk - yk;
ek1_1 <= ek1;
ek1_2 <= ek1_1;
ek1_acc <= ek1+ek1_1+ek1_2;
temp2 <= '0';
END IF;
END IF;
END PROCESS;
end behavior;
但是我仿真的結果不一致，總感覺代碼哪兒有問題，但是不知道怎么改，找不出問題在哪兒，求大神指教
下面是我的modelsim仿真結果
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