FPGA按鍵去抖操作
目標
- Verilog編程語言，實作按鍵去抖，
- 模塊：key_delay，模塊可以輸入按鍵去抖延遲時間引數，
- 輸入：時鐘、復位、按鍵信號 key_in
- 輸出：去抖后的按鍵信號 key_out
代碼
- 模塊實作代碼：
module key_delay
#(
parameter FREQ = 200 ,//MHz, 晶振頻率
parameter DLY_TIME = 20_000 //us, 按鍵延遲時間
)
(
input sys_clk_p ,
input sys_clk_n ,
input rst_n ,
input key_in ,
output reg key_out
);
localparam MAX_TIME = FREQ * DLY_TIME;//延時時間對應計數值
wire clk200M ;
reg [31:0] cnt ;
wire max_flag ;//計數器達到最大值
reg key_in_r1 ;//按鍵key_in節拍
reg key_in_r2 ;
wire key_act ;//按鍵動作標志
//clk200M, 原語，差分時鐘轉單端
IBUFDS
#(
.DIFF_TERM ("FALSE" ),// Differential Termination
.IBUF_LOW_PWR ("TRUE" ),// Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD ("DEFAULT" ) // Specify the input I/O standard
) IBUFDS_inst
(
.O (clk200M ),// Buffer output
.I (sys_clk_p ),// Diff_p buffer input (connect directly to top-level port)
.IB (sys_clk_n ) // Diff_n buffer input (connect directly to top-level port)
);
//key_in_r1, key_in_r2，打節拍
always @(posedge clk200M) begin
key_in_r1 <= key_in;
key_in_r2 <= key_in_r1;
end
//key_act, 按鍵有動作
assign key_act = key_in_r1 ^ key_in_r2;
//max_flag, 計數達到最大值
assign max_flag = (cnt == MAX_TIME) ? 1'b1 : 1'b0;
//cnt
always @(posedge clk200M) begin
case({key_act, max_flag})
2'b00://按鍵無動作， 且計數未達到最大值
cnt <= cnt + 'd1;
2'b01://按鍵無動作， 且計數達到最大值
cnt <= cnt;
default://按鍵有動作
cnt <= 'd0;
endcase
end
//key_out
always @(posedge clk200M or negedge rst_n) begin
if(~rst_n)
key_out <= key_in_r2;
else if(cnt == MAX_TIME)
key_out <= key_in_r2;
else
key_out <= key_out;
end
endmodule
*仿真代碼
`timescale 1ns / 1ps
module tb_key_delay;
reg sys_clk_p;
wire sys_clk_n;
reg rst_n;
reg key_in;
wire key_out;
//-----------------------------------------------
integer i;
key_delay
#(
.FREQ (200 ),//MHz, 晶振頻率
.DLY_TIME (1 ) //us, 按鍵延遲時間
)
inst_key_delay
(
.sys_clk_p (sys_clk_p ),
.sys_clk_n (sys_clk_n ),
.rst_n (rst_n ),
.key_in (key_in ),
.key_out (key_out )
);
initial begin
sys_clk_p = 0;
rst_n = 0;
key_in = 0;
#100;
rst_n = 1;
#100;
for(i = 0; i <= 10; i = i + 1) begin
key_in = ~key_in;
#30;
end
#1500;
for(i = 0; i <= 10; i = i + 1) begin
key_in = ~key_in;
#30;
end
#1500;
for(i = 0; i <= 10; i = i + 1) begin
key_in = ~key_in;
#30;
end
end
//時鐘
always #2.5 sys_clk_p = ~sys_clk_p;
assign sys_clk_n = ~sys_clk_p;
endmodule
- 仿真結果
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