計數器

寫在前面

1. 計數器是數字系統和計算機系統常用的基本模塊，是計數暫存器的簡稱
2. 74LS161模塊是一個同步加法計數器（通用計數器）

下圖為其的介面描述

下圖為功能描述

進入正題

廢話不多說，我們進入正題——74LS161的設計：
開門見山給出我的Verilog代碼（經過仿真驗證過）：

module My74LS161(
    input CP,CR,
    input CTP,CTT,
    input L_D,
    input [3:0] D,
    output reg [3:0] Q,
    output CO
);
    parameter State_0 = 4'b0000,State_1 = 4'b0001,State_2 = 4'b0010,State_3 = 4'b0011,State_4 = 4'b0100,State_5 = 4'b0101,State_6 = 4'b0110,State_7 = 4'b0111,State_8 = 4'b1000,State_9 = 4'b1001,State_10 = 4'b1010,State_11 = 4'b1011,State_12 = 4'b1100,State_13 = 4'b1101,State_14 = 4'b1110,State_15 = 4'b1111;

    always @(posedge CP,negedge CR) begin
        if(~CR) begin
            Q <= 0;
        end		
        else 
            if(~L_D) begin
                Q <= D;
            end
        else begin
            if(CTT & CTP)
                begin
                    case(Q)
                        State_0 : Q <= State_1;
                        State_1 : Q <= State_2;
                        State_2 : Q <= State_3;
                        State_3 : Q <= State_4;
                        State_4 : Q <= State_5;
                        State_5 : Q <= State_6;
                        State_6 : Q <= State_7;
                        State_7 : Q <= State_8;
                        State_8 : Q <= State_9;
                        State_9 : Q <= State_10;
                        State_10 : Q <= State_11;
                        State_11 : Q <= State_12;
                        State_12 : Q <= State_13;
                        State_13 : Q <= State_14;
                        State_14 : Q <= State_15;
                        State_15 : Q <= State_0;
                    endcase
                end
        end
    end

    assign CO = (&Q) &CTT;
endmodule

實作思想是：有限狀態機，這里一共0~15，十六個狀態，實作這些狀態之間的相互轉換即可，當然也可以通過其他方法給出，

順便給出我的仿真代碼

initial begin
    CR = 0;
    D = 0;
    CTP = 0;
    CTT = 0;
    L_D = 0;

    #100;
    CR = 1;
    L_D= 1;
    D = 4'b1100;
    CTT = 0;
    CTP = 0;

    #30 CR = 0;
    #20 CR = 1;
    #10 L_D = 0;
    #30 CTT = 1;
    CTP = 1;
    #10 L_D = 1;

    #510;
    CR = 0;
    #20 CR = 1;
    #500;
end
always begin
    CP = 0;#20;
    CP = 1;#20;
end

仿真結果（ISE）

24,60進制計數器

設計好了74LS141模塊后，就可以設計24,60進制計數器了，這里給出電路圖

實際上我們可以通過兩個74LS161模塊搭成24進制計數器，這里我們采用BCD編碼，也就是說個位是逢9清零或者是碰到23就清零，十位是碰到23清零，
可以采取兩個與非門用來檢測這個9或者23，從而判斷是否清零，
獻上代碼：

module Counter_24(
		input clk,
		input rst,
		output C24,
		output [7:0] Q );	//BCD編碼，Q[7:4]是十位數，Q[3:0]是個位數
		
		wire LD1;
		wire CT;
		wire NAND_1,NAND_2;
		assign NAND_1 = ~(Q[0]&Q[3]);		//檢測9的出現
		assign NAND_2 = ~(Q[0]&Q[1]&Q[5]);	//檢測23的出現
		assign LD1 = NAND_1 & NAND_2;
		assign C24 = NAND_2;
		assign CT = ~NAND_1;
		
	//兩個74LS161分別計數
	My74LS161 m1 (.CP(clk),.CR(rst),
     .CTP(1'b1),.CTT(1'b1),
     .L_D(LD1),
	  .D(4'b0000),
     .Q({Q[3],Q[2],Q[1],Q[0]})
	  );
	  
	My74LS161 m2 (.CP(clk),.CR(rst),
     .CTP(CT),.CTT(CT),
     .L_D(NAND_2),
	  .D(4'b0000),
     .Q({Q[7],Q[6],Q[5],Q[4]})
	  );

endmodule

同理，獻上60進制計數器

module Counter_60(
		input clk,
		input rst,
		output C60,
		output [7:0] Q );
		
		wire LD1;
		wire CT;
		wire NAND_1,NAND_2;
		assign NAND_1 = ~(Q[0]&Q[3]);
		assign NAND_2 = ~(Q[5]&Q[6]);
		assign LD1 = NAND_1 & NAND_2;
		assign C60 = NAND_2;
		assign CT = ~NAND_1;
		
	My74LS161 m1 (.CP(clk),.CR(rst),
     .CTP(1'b1),.CTT(1'b1),
     .L_D(LD1),
	  .D(4'b0000),
     .Q({Q[3],Q[2],Q[1],Q[0]})
	  );
	  
	My74LS161 m2 (.CP(clk),.CR(rst),
     .CTP(CT),.CTT(CT),
     .L_D(NAND_2),
	  .D(4'b0000),
     .Q({Q[7],Q[6],Q[5],Q[4]})
	  );

endmodule