實作急用固定脈沖實作LED的控制，觸發信號如仿真結果中的clk和sda所示，已用示波器觀察過，功能仿真結果也如圖，代碼如下，求高人指點！
報警提示:1.interring latches for variable “s1“和"s2",which holds its previous value in one or more paths through the always construct
2.timequest timing analyzer is analyzing 2 combinational loops as latches.
3. Timing requirements not met.
module fp_verilog(
clk,rst_n,
sda,
led,data_r,state_r
);
input clk; //時鐘信號 SCL
input rst_n; //復位信號 低電平有效
input sda; //資料信號 SDA
output led; //指示燈 1-亮 0-滅
output data_r;
output state_r;
wire[1:0] data_r;
reg s1;
always @(negedge sda or negedge clk or negedge rst_n)
if(!rst_n) s1 <= 1'b0;
else if(!sda)
begin
if(clk==1'b1) s1 <= 1'b1;
else if(clk==1'b0) s1<=1'b0;
end
reg s2;
always @(posedge sda or negedge clk or negedge rst_n)
if(!rst_n) s2 <= 1'b0;
else if(sda)
begin
if(clk==1'b1) s2 <= 1'b1;
else if(clk==1'b0) s2<=1'b0;
end
reg state;
always @(posedge s1 or posedge s2 or negedge rst_n)
if(!rst_n) state <= 1'b0;
else if(s1) state <= 1'b1;
else if(s2) state <= 1'b0;
reg[1:0] data;
reg[1:0] k;//0-3
always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
data[1:0] <= 2'b11;
k<=2'd0;
end
else if(state)
begin
data[k]<=sda;
if(k==2'd1) k<=2'd0;
else k<=k+2'd1;
end
else begin
data[1:0]<=2'b11;
k<=2'd0;
end
reg led_r;
always @(negedge state or negedge rst_n)
if(!rst_n) led_r <= 1'b0;
else if(data=https://bbs.csdn.net/topics/=2'b01) led_r <= 1'b1;
else if(data=https://bbs.csdn.net/topics/=2'b00) led_r <= 1'b0;
/*
always @(data)
if(data=https://bbs.csdn.net/topics/=2'b11) led_r<=1'b0;
else if(data=https://bbs.csdn.net/topics/=2'b01) led_r<=1'b1;
else if(data=https://bbs.csdn.net/topics/=2'b00) led_r <= 1'b0;
*/
assign led = led_r;
assign data_r=data;
assign state_r=state;
endmodule
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標籤：硬件設計
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