ARM - Advanced SIMD register - quadword (128 bits wide) and doubleword (64 bits wide)
1. Bytes, Halfwords, and Words
Byte
Eight bits (8 bits).
Halfword
Two bytes (16 bits).
Word
Four bytes (32 bits).
Quadword
16 contiguous bytes (128 bits).
2. Register encoding
Advanced SIMD registers are either quadword (128 bits wide) or doubleword (64 bits wide). Some instructions have options for either doubleword or quadword registers. This is normally encoded in Q (bit [6]) as Q = 0 for doubleword operations, Q = 1 for quadword operations.
一些指令具有雙字或四字暫存器的選項，通常，它以 Q (bit [6]) 編碼，對于雙字操作，Q = 0，對于四字操作，Q = 1，
References
ARM Cortex-A Series Programmer’s Guide for ARMv8-A
https://developer.arm.com/documentation/den0024/a/Porting-to-A64/Data-types
RealView Platform Baseboard for Cortex-A8 User Guide
https://developer.arm.com/documentation/dui0417/d/preface/about-this-book/other-conventions
ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
https://developer.arm.com/documentation/ddi0406/b/Application-Level-Architecture/Advanced-SIMD-and-VFP-Instruction-Encoding/Register-encoding
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