1.
module FSM_Welcome(
clk,
rst_n,
data,
start,
num
);
input clk;
input rst_n;
input [7:0]data;
input start; //使能信號
output reg [2:0]num; //需要檢測的序列出現的次數
reg [3:0]state;
localparam
check_W = 4'd1, //檢測W
check_e0 = 4'd2, //檢測第一個e
check_l = 4'd3, //檢測l
check_c = 4'd4, //檢測c
check_o = 4'd5, //檢測o
check_m = 4'd6, //檢測m
check_e1 = 4'd7; //檢測第二個e
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
state <= check_W;
num <= 3'd0;
end
else if(start)
begin
case(state)
check_W: begin
if(data == "W")
state <= check_e0;
else
state <= check_W;
end
check_e0: begin
if(data == "e")
state <= check_l;
else if(state == "W")
state <= check_e0;
else
state <= check_W;
end
check_l: begin
if(data == "l")
state <= check_c;
else if(state == "W")
state <= check_e0;
else
state <= check_W;
end
check_c: begin
if(data == "c")
state <= check_o;
else if(state == "W")
state <= check_e0;
else
state <= check_W;
end
check_o: begin
if(data == "o")
state <= check_m;
else if(state == "W")
state <= check_e0;
else
state <= check_W;
end
check_m: begin
if(data == "m")
state <= check_e1;
else if(state == "W")
state <= check_e0;
else
state <= check_W;
end
check_e1: begin
if(data == "e")
begin
state <= check_W;
num <= num + 1'd1;
end
else if(state == "W")
state <= check_e0;
else
state <= check_W;
end
default: state <= check_W;
endcase
end
endmodule
2.測驗檔案
`timescale 1ns/1ns
`define clk_period 20
module FSM_Welcome_tb;
reg clk;
reg rst_n;
wire [7:0]data;
reg start;
wire [2:0]num;
//wire flag;
wire [511:0]data_tmp;
reg [511:0]data_reg;
assign data_tmp = "abcdeWelcomehijkWelcomedcba";
always@(posedge clk or negedge rst_n)
if(!rst_n)
data_reg <= 0;
else if(start)
data_reg <= data_reg << 8;
else
data_reg <= data_tmp;
assign data = data_reg[511:504];
FSM_Welcome FSM_Welcome(.clk(clk),.rst_n(rst_n),.data(data),.start(start),.num(num));
initial clk = 1;
always#(`clk_period/2)clk = ~clk;
initial begin
rst_n = 0;
start = 0;
#(`clk_period*20)
rst_n = 1;
#(`clk_period*10)
start = 1;
#(`clk_period*64)
#200;
$stop;
end
endmodule
3.不出波形
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標籤：硬件設計