library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sipo is
port(rst,din,clk:in std_logic;
dout:out std_logic_vector(1 downto 0));
end sipo;
architecture behav of sipo is
signal q:std_logic_vector(1 downto 0);
begin
process(clk,q,din,rst)
variable t:integer range 1 to 3;
begin
if rst='1' then dout<="00";
else if (t=3)then
t:=1;
dout<=q;
elsif(clk'event and clk='1')then
t:=t+1;
q(0)<=din;
q(1)<=q(0);
end if;
end if;
end process;
end behav;
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