第三題，查了資料，是這么說的CPU 會**完成**那條已**finish** MEM stage的指令。然后將exception victim定位在下一條(following)指令上。那么怎么回答 2 3 問呢。
關于第四題，我查詢資料，我覺得兩個小問，ALU overflow都具有高優先級，請問對嗎？
謝謝
3. A processor is executing code and executes a divide instruction that divides by zero.
(a)Describe in the MIPS instruction set what state needs to be saved by the hardware interrupt mechanism.
(b)Assume that the interrupt handler reads registers R5, R6, R7 and writes registers R5, R8, R10.What registers does the interrupt handler need to save?
(c)What state does the ERET instruction change?
4.An instruction takes the following synchronous exceptions: Instruction Address Exception, ALU Overflow. What should the interrupt cause be loaded with? What if that same instruction has an external interrupt pending? Explain your reasoning?
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