早些時候還是可以看到正常的仿真，正計時，暫停和倒計時的波形
現在是這樣的錯誤報告
以下是代碼：
功能實作見圖片
`timescale 1ns / 1ps
module stopwatch(clk,rst,sw,m1,m2,s1,s2);
input clk,rst;
output reg m1,m2,s1,s2; // 1表示十位,2表示個位
input [2:0]sw;//按鍵低電平表示按下 2:min,1:sec,0:pause/start
parameter count_on=3'd0,settime=3'd1,pause=3'd2,clear=3'd3,count_down=3'd4;
parameter a=3'b000,b=3'b001,c=3'b010,d=3'b100,e=3'b011,f=3'b101,g=3'b110,h=3'b111;
reg [2:0]mode;
always@(posedge clk)begin
case(sw)
a:begin mode<=clear; end
b:begin mode<=clear; end
e:begin mode<=settime; end
f:begin mode<=settime;end
g:if(mode==count_on) begin mode<=pause; end
else if(mode==pause) begin mode<=count_on; end
else if(mode==settime) begin mode<=count_down; end
else if(mode==count_down) begin mode<=pause;end
else if(mode==clear) begin mode<=count_on; end
h:begin mode<=pause; end
default:begin mode<=pause; end
endcase
end
always@(posedge clk)begin
case(mode)//
count_on://計時s
begin
if (!rst) s2<=s2;
else if(s2==9)
s2<=0;
else
s2<=s2+1;
if(!rst) s1<=s1;
else if(s2==9)
begin
if(s1==5)
s1<=0;
else
s1<=s1+1;
end
//--------------------------計時部分m
if(!rst) m2<=m2;
else if(s1==5&&s2==9)
begin
if(m2==9)
m2<=0;
else
m2<=m2+1;
end
if(!rst) m1<=m1;
else if(s1==5&&s2==9)
begin
if(m2==9)
begin
if(m1==9)
m1<=0;
else
m1<=m1+1;
end
end
end
//---------------------------------------------------
//----------------------- 倒計時輸入部分
settime:
begin
s1<=0;s2<=0;m1<=0;m2<=0;
if(sw[1]==0) begin
begin//if3
if(s1!=5) begin//if2
if(s2!=9) begin s2<=s2+1; end//if1
else begin s2<=0; s1<=s1+1; end
end//else1
else begin s1<=0; end //else2
end
if(sw[2]==0) begin
if(m1!=9) begin//if2
if(m2!=9) begin m2<=m2+1; end//if1
else begin m2<=0; m1<=m1+1; end
end//else1
else begin m1<=0; end //else2
end
end
end
//------------倒計時m1 m2:s1 s2 12:30
count_down:
begin//0
if(s1==0&s2==0&m1==0&m2==0) begin mode<=clear; end
else if(!rst)
begin//1
if(s2!=0) begin//2
if(s1!=0) begin//3
if(m2!=0) begin//4
if(m1!=0) begin s2=s2-1; end
else if(s1!=0) begin s2<=9;s1<=s1-1;end
else if(m2!=0) begin s1<=5; m2<=m2-1;end
else begin m2<=9; m1<=m1-1; end//3
end//2
end//1
end //0
end
end
//--------------------------
//------------清零，停止計時。
clear :
begin
s1<=0;s2<=0;m1<=0;m2<=0;
end
//------------暫停鍵，停止計時
pause:
begin
s1<=s1;s2<=s2;m1<=m1;m2<=m2;
end
endcase
end
endmodule
仿真模塊：
`timescale 1ns / 1ps
//test for pause and count
module test();
reg clk,rst;
reg sw;
wire[3:0] m1,m2,s1,s2;
stopwatch u1(clk,rst,m1,m2,s1,s2,sw);
always #5 clk=~clk;
initial
begin
clk=0;
rst=0;
#10 rst=1;
sw=3'b001;//reset
#200 sw=3'b110; //計時開始
#300 sw=3'b111;//300s以后制7，暫停
#1000 sw=3'b110;//200以后開始
#2000 sw=3'b111;//1000以后暫停
#5100 sw=3'b001;
#9000 sw=3'b110;
end
endmodule
轉載請註明出處，本文鏈接：https://www.uj5u.com/qita/71014.html
標籤：硬件設計