源代碼如下
module dot_array_driver
(
input clk,
input rst_n,
input [3:0] sw1,
input [3:0] sw2,
output reg [7:0] colr,
output reg [7:0] colg,
output reg [7:0] row
);
localparam s0 = 3'd0, s1 = 3'd1, s2 = 3'd2, s3 = 3'd3,
s4 = 3'd4, s5 = 3'd5, s6 = 3'd6, s7 = 3'd7;
reg [12:0] cnt;
always @(posedge clk or negedge rst_n)
if(!rst_n) cnt <= 1'b0;
else if(cnt >= 16'd62499) cnt <= 1'b0;
else cnt <= cnt + 1'b1;
reg clk_800hz;
always @(posedge clk or negedge rst_n)
if(!rst_n) clk_800hz <= 1'b0;
else if(cnt == 16'd62499) clk_800hz <= ~clk_800hz;
else clk_800hz <= clk_800hz;
reg [63:0] mem [9:0];
always begin
mem[0]= {8'h00, 8'h00, 8'h00, 8'h18, 8'h18, 8'h00, 8'h00, 8'h00}; // 0
mem[1]= {8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00, 8'h00}; // 1
mem[2]= {8'h00, 8'h3c, 8'h42, 8'h5a, 8'h5a, 8'h42, 8'h3c, 8'h00}; // 2
mem[3]= {8'h36, 8'h80, 8'h99, 8'h25, 8'ha4, 8'h99, 8'h01, 8'h6c}; // 3 紅色
mem[4]= {8'h00, 8'h00, 8'h00, 8'h18, 8'h18, 8'h00, 8'h00, 8'h00}; // 4
mem[5]= {8'h00, 8'h00, 8'h18, 8'h24, 8'h24, 8'h18, 8'h00, 8'h00}; // 5
mem[6]= {8'h00, 8'h00, 8'h00, 8'h18, 8'h18, 8'h00, 8'h00, 8'h00}; // 6
mem[7]= {8'h6c, 8'h01, 8'h99, 8'ha4, 8'h25, 8'h99, 8'h80, 8'h36}; // 7 綠色
mem[8]= {8'h00, 8'h00, 8'h36, 8'h49, 8'h49, 8'h49, 8'h36, 8'h00}; // 8
mem[9]= {8'h00, 8'h00, 8'h06, 8'h49, 8'h49, 8'h29, 8'h1E, 8'h00}; // 9
end
reg [2:0] state;
always @(posedge clk_800hz or negedge rst_n)
if(!rst_n) begin state <= s0; row <= 8'hff; colr = 8'hff;colr = 8'hff; end
else case(state)
s0: begin row <= 8'b1111_1110; colr = ~mem[sw1][56+:8];colg = ~mem[sw2][56+:8] ;state <= s1; end
s1: begin row <= 8'b1111_1101; colr = ~mem[sw1][48+:8];colg = ~mem[sw2][56+:8] ;state <= s2; end
s2: begin row <= 8'b1111_1011; colr = ~mem[sw1][40+:8];colg = ~mem[sw2][56+:8] ;state <= s3; end
s3: begin row <= 8'b1111_0111; colr = ~mem[sw1][32+:8];colg = ~mem[sw2][56+:8] ;state <= s4; end
s4: begin row <= 8'b1110_1111; colr = ~mem[sw1][24+:8];colg = ~mem[sw2][56+:8] ;state <= s5; end
s5: begin row <= 8'b1101_1111; colr = ~mem[sw1][16+:8];colg = ~mem[sw2][56+:8] ;state <= s6; end
s6: begin row <= 8'b1011_1111; colr = ~mem[sw1][ 8+:8];colg = ~mem[sw2][56+:8] ;state <= s7; end
s7: begin row <= 8'b0111_1111; colr = ~mem[sw1][ 0+:8];colg = ~mem[sw2][56+:8] ;state <= s0; end
default: begin state <= s0; row <= 8'hff; colr = 8'hff; colg = 8'hff; end
endcase
endmodule
module newyear
(input clk,
input rst_n,
output wire [7:0] row,
output wire [7:0] colr,
output wire [7:0] colg
);
reg [12:0] cnt;
always @(posedge clk )
if(!rst_n) cnt <= 1'b0;
else if(cnt >= 24'd12_499_999) cnt <= 1'b0;
else cnt <= cnt + 1'b1;
reg clk_4hz;
always @(posedge clk )
if(!rst_n) clk_4hz <= 1'b0;
else if(cnt == 24'd12_499_999) clk_4hz <= ~clk_4hz;
else clk_4hz <= clk_4hz;
reg [2:0] state;
reg [3:0]sw1 ;
reg [3:0]sw2 ;
dot_array_driver driver(clk,rst_n,sw1,sw2,colr,colg,row);
always @(posedge clk_4hz or negedge rst_n)
if(!rst_n) begin state <= 0; end
else case (state)
0: begin sw1<=0 ;sw2<=4;state <= 1; end
1: begin sw1<=1 ;sw2<=5;state <= 2; end
2: begin sw1<=2 ;sw2<=6;state <= 3; end
3: begin sw1<=3 ;sw2<=7;state <= 0; end
default: begin state <= 0; end
endcase
endmodule
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