初學VHDL,我知道只要把15.16位添加00就好了 ,可是不知道如何添加.我無論把"input1 : std_logic_vector(15 downto 0);"放在任何地方都會報錯
這是代碼
library ieee;
use ieee.std_logic_1164.all;
entity tristate_buffer16 is
port( input : in std_logic_vector(13 downto 0);
enable : in std_logic;
output : out std_logic_vector(15 downto 0));
end tristate_buffer16;
architecture behav of tristate_buffer16 is
begin
process( input, enable)
begin
if(enable = '1') then
input1 <= (1 downto 0 => '0') & input;
output <=input1 ;
else
output <= "ZZZZZZZZZZZZZZZZ";
end if;
end process;
end behav;
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------------------------------------------------------------------------------------ Company:
-- Engineer:
--
-- Create Date: 11:41:27 09/09/2019
-- Design Name:
-- Module Name: Tribuf - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Tribuf is
Port ( IOin : in STD_LOGIC_VECTOR (15 downto 0);
IOen : in STD_LOGIC;
IOout : out STD_LOGIC_VECTOR (15 downto 0));
end Tribuf;
architecture Behavioral of Tribuf is
begin
IOout <= IOin when IOen ='1' else "ZZZZZZZZZZZZZZZZ";
end Behavioral;
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