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MIPS Branch Target Buffer動態分支預測（BTB）

2020-09-14 14:10:25 軟體設計

MIPS代碼：

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/07/23 15:31:35
// Design Name: 
// Module Name: MIPS
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module MIPS(
input clk,
input rst
    );
reg [31:0] RegFile [0:31];
reg [31:0] IMEM [0:255];
reg [31:0] DMEM [0:255];

integer i;
initial
begin
    for(i=0;i<256;i=i+1)
        DMEM[i]=i;
end

initial
begin
    for(i=0;i<32;i=i+1)
        RegFile[i]<=i;
end

initial
begin
    IMEM[0]=32'h00240820;
    IMEM[4]=32'h01024022;
    IMEM[8]=32'h1100fffd;
    IMEM[12]=32'h00c72820;
    IMEM[16]=32'h014b4820;
    IMEM[20]=32'h01ae6020;
    IMEM[24]=32'h02117820;
end

wire IF2ID_Write;
wire PCWrite;
wire ID2EXE_Stall;
wire [31:0]ALUSrcA;                  
wire [31:0]ALUSrcB;
wire [1:0]ForwardA;
wire [1:0]ForwardB;
wire [4:0]IF2ID_rs;
wire [4:0]IF2ID_rt;
wire [31:0]MEM2WB_Data;
wire FlushIF;
wire FlushID;
wire FlushEXE;

assign FlushIF=(EXE2MEM_Branch==1'b1&&(EXE2MEM_ALUOut!=EXE2MEM_predicted))?1'b1:1'b0;           //若預測錯誤，則flush之前的3條指令
assign FlushID=(EXE2MEM_Branch==1'b1&&(EXE2MEM_ALUOut!=EXE2MEM_predicted))?1'b1:1'b0;
assign FlushEXE=(EXE2MEM_Branch==1'b1&&(EXE2MEM_ALUOut!=EXE2MEM_predicted))?1'b1:1'b0;

reg wr_req;
reg [31:0]wr_PC;
reg [31:0]wr_predicted_PC;
reg wr_predicted_state_bit;
reg [31:0]rd_PC;

wire rd_predicted_PC;
wire rd_predicted;

reg IF2ID_predicted;
reg ID2EXE_predicted;
reg EXE2MEM_predicted;


//更新BTB
always@(*)
if(EXE2MEM_Branch)
    if(EXE2MEM_ALUOut==1'b0&&EXE2MEM_predicted==1'b1)     //預測taken但不taken
    begin
        wr_req=1'b1;
        wr_PC=EXE2MEM_NPC-32'd4;
        wr_predicted_PC=EXE2MEM_BranchPC;
        wr_predicted_state_bit=1'b0;
    end
    else if(EXE2MEM_ALUOut==1'b1&&EXE2MEM_predicted==1'b0)    //預測不taken但taken
    begin
        wr_req=1'b1;
        wr_PC=EXE2MEM_NPC-32'd4;
        wr_predicted_PC=EXE2MEM_BranchPC;
        wr_predicted_state_bit=1'b1;
    end
    else
    begin
        wr_req=1'b0;
        wr_PC=EXE2MEM_NPC-32'd4;
        wr_predicted_PC=EXE2MEM_BranchPC;
        wr_predicted_state_bit=1'b0;
    end
else
begin
    wr_req=1'b0;
    wr_PC=EXE2MEM_NPC-32'd4;
    wr_predicted_PC=EXE2MEM_BranchPC;
    wr_predicted_state_bit=1'b0;
end
//傳遞rd_predicted,即預測結果，以與之后的實際結果相比較
always@(posedge clk,posedge rst)
if(rst)
begin
    IF2ID_predicted<=1'b0;
    ID2EXE_predicted<=1'b0;
    EXE2MEM_predicted<=1'b0;
end
else
begin
    IF2ID_predicted<=rd_predicted;
    ID2EXE_predicted<=IF2ID_predicted;
    EXE2MEM_predicted<=ID2EXE_predicted;
end


//IF
reg [31:0] PC;
reg [31:0] IF2ID_NPC;
reg [31:0] IF2ID_IR;
//ID
reg [4:0]ID2EXE_rs;                //Rs暫存器號 約定大寫為資料，小寫為暫存器�?
reg [4:0]ID2EXE_rt;                //Rt暫存器號
reg [4:0]ID2EXE_rd;                //Rd暫存器號
reg [31:0]ID2EXE_Rs;               //Rs暫存器內�?
reg [31:0]ID2EXE_Rt;               //Rt暫存器內�?
reg [31:0]ID2EXE_Imm;              //符號擴展后的立即�?
reg [31:0]ID2EXE_NPC;                  

reg ID2EXE_RegDst;
reg ID2EXE_ALUSrc;
reg ID2EXE_MemRead;
reg ID2EXE_MemWrite;
reg ID2EXE_Branch;
reg ID2EXE_MemtoReg;
reg ID2EXE_RegWrite;
reg [1:0] ID2EXE_ALUOp;
//EXE
reg [31:0]EXE2MEM_ALUOut;
reg [31:0]EXE2MEM_BranchPC;
reg [31:0]EXE2MEM_Rt;
reg [4:0]EXE2MEM_RegRd;                    //WB階段寫暫存器�?

reg EXE2MEM_MemRead;
reg EXE2MEM_MemWrite;
reg EXE2MEM_Branch;
reg EXE2MEM_MemtoReg;
reg EXE2MEM_RegWrite;
reg [31:0]EXE2MEM_NPC;
//MEM
reg [31:0]MEM2WB_LDM;
reg [31:0]MEM2WB_ALUOut;
reg [4:0]MEM2WB_RegRd;

reg MEM2WB_RegWrite;
reg MEM2WB_MemtoReg;

/****************************************************************************************/

assign IF2ID_rs=IF2ID_IR[25:21];
assign IF2ID_rt=IF2ID_IR[20:16];
assign MEM2WB_Data=(MEM2WB_MemtoReg)?MEM2WB_LDM:MEM2WB_ALUOut;

//IF
BTB V(
.clk(clk),
.rst(rst),
.rd_PC(PC),
.rd_predicted(rd_predicted),
.rd_predicted_PC(rd_predicted_PC),
.wr_req(wr_req),
.wr_PC(wr_PC),
.wr_predicted_PC(wr_predicted_PC),
.wr_predicted_state_bit(wr_predicted_state_bit)
);

always@(posedge clk,posedge rst)
begin
if(rst)
begin
    PC<=32'd0;
    IF2ID_NPC<=32'd0;
    IF2ID_IR<=32'd0;
end
else
begin
    if(PCWrite)
    begin
        if(EXE2MEM_Branch)
            if(EXE2MEM_predicted==1'b1&&EXE2MEM_ALUOut==1'b0)           //預測taken但實際沒tabke
                PC<=EXE2MEM_NPC;
            else if(EXE2MEM_predicted==1'b0&&EXE2MEM_ALUOut==1'b1)      //預測not taken但實際taken
                PC<=EXE2MEM_BranchPC;
            else if(rd_predicted)
                PC<=rd_predicted_PC;
            else
                PC<=PC+32'd4;
        else if(rd_predicted)
            PC<=rd_predicted_PC;
        else
            PC<=PC+32'd4;
    end
    else
        PC<=PC;
    if(FlushIF)
    begin
        IF2ID_NPC<=32'd0;
        IF2ID_IR<=32'd0;
    end
    else if(IF2ID_Write)
    begin
        IF2ID_NPC<=PC+4;
        IF2ID_IR<=IMEM[PC];
    end
    
    else
    begin
        IF2ID_NPC<=IF2ID_NPC;
        IF2ID_IR<=IF2ID_IR;
    end
end
end

//ID
HAZARD_DETECTION U1(
.ID2EXE_MemRead(ID2EXE_MemRead),
.IF2ID_rs(IF2ID_rs),
.IF2ID_rt(IF2ID_rt),
.ID2EXE_rt(ID2EXE_rt),
.PCWrite(PCWrite),
.ID2EXE_Stall(ID2EXE_Stall),
.IF2ID_Write(IF2ID_Write)
);

always@(posedge clk,posedge rst)
if(rst)
begin
    ID2EXE_RegDst<=1'b0;
    ID2EXE_ALUSrc<=1'b0;
    ID2EXE_ALUOp<=2'b00;
    ID2EXE_MemRead<=1'b0;
    ID2EXE_MemWrite<=1'b0;
    ID2EXE_Branch<=1'b0;
    ID2EXE_RegWrite<=1'b0;
    ID2EXE_MemtoReg<=1'b0;
end
else if(ID2EXE_Stall||FlushID)
begin
    ID2EXE_RegDst<=1'b0;
    ID2EXE_ALUSrc<=1'b0;
    ID2EXE_ALUOp<=2'b00;
    ID2EXE_MemRead<=1'b0;
    ID2EXE_MemWrite<=1'b0;
    ID2EXE_Branch<=1'b0;
    ID2EXE_RegWrite<=1'b0;
    ID2EXE_MemtoReg<=1'b0;
end
else
case(IF2ID_IR[31:26])
6'b000000:begin
    {ID2EXE_RegDst,ID2EXE_ALUSrc,ID2EXE_MemtoReg,ID2EXE_RegWrite,ID2EXE_MemRead,
    ID2EXE_MemWrite,ID2EXE_Branch,ID2EXE_ALUOp}<=9'b100100010;
end
6'b100011:begin
    {ID2EXE_RegDst,ID2EXE_ALUSrc,ID2EXE_MemtoReg,ID2EXE_RegWrite,ID2EXE_MemRead,
    ID2EXE_MemWrite,ID2EXE_Branch,ID2EXE_ALUOp}<=9'b011110000;
end
6'b101011:begin
    {ID2EXE_RegDst,ID2EXE_ALUSrc,ID2EXE_MemtoReg,ID2EXE_RegWrite,ID2EXE_MemRead,
    ID2EXE_MemWrite,ID2EXE_Branch,ID2EXE_ALUOp}<=9'b010001000;
end
6'b000100:begin
    {ID2EXE_RegDst,ID2EXE_ALUSrc,ID2EXE_MemtoReg,ID2EXE_RegWrite,ID2EXE_MemRead,
    ID2EXE_MemWrite,ID2EXE_Branch,ID2EXE_ALUOp}<=9'b000000101;
end
default:
    {ID2EXE_RegDst,ID2EXE_ALUSrc,ID2EXE_MemtoReg,ID2EXE_RegWrite,ID2EXE_MemRead,
    ID2EXE_MemWrite,ID2EXE_Branch,ID2EXE_ALUOp}<=9'b000000000;
endcase

always@(posedge clk,posedge rst)
if(rst)
begin
    ID2EXE_rs<=5'd0;
    ID2EXE_rt<=5'd0;
    ID2EXE_rd<=5'd0;
    ID2EXE_Rs<=32'd0;
    ID2EXE_Rt<=32'd0;
    ID2EXE_Imm<=32'd0;
    ID2EXE_NPC<=32'd0;
end
else if(FlushID)
begin
    ID2EXE_rs<=5'd0;
    ID2EXE_rt<=5'd0;
    ID2EXE_rd<=5'd0;
    ID2EXE_Rs<=32'd0;
    ID2EXE_Rt<=32'd0;
    ID2EXE_Imm<=32'd0;
    ID2EXE_NPC<=32'd0;
end
else
begin
    ID2EXE_rs<=IF2ID_IR[25:21];
    ID2EXE_rt<=IF2ID_IR[20:16];
    ID2EXE_rd<=IF2ID_IR[15:11];
    ID2EXE_Rs<=RegFile[IF2ID_IR[25:21]];
    ID2EXE_Rt<=RegFile[IF2ID_IR[20:16]];
    ID2EXE_Imm<={{16{IF2ID_IR[15]}},IF2ID_IR[15:0]};
    ID2EXE_NPC<=IF2ID_NPC;
end

//EXE

FORWARDING U2(
.ID2EXE_rs(ID2EXE_rs),
.ID2EXE_rt(ID2EXE_rt),
.EXE2MEM_RegRd(EXE2MEM_RegRd),
.MEM2WB_RegRd(MEM2WB_RegRd),
.EXE2MEM_RegWrite(EXE2MEM_RegWrite),
.MEM2WB_RegWrite(MEM2WB_RegWrite),
.ForwardA(ForwardA),
.ForwardB(ForwardB)
);
//ALUSrcA三�?�一
mux3_1 U3(
.a(ID2EXE_Rs),
.b(EXE2MEM_ALUOut),
.c(MEM2WB_Data),
.select(ForwardA),
.out(ALUSrcA)
);
//ALUSrcB
mux3_1 U4(
.a(ID2EXE_Rt),
.b(EXE2MEM_ALUOut),
.c(MEM2WB_Data),
.select(ForwardB),
.out(ALUSrcB)
);

always@(posedge clk,posedge rst)
if(rst)
begin
    EXE2MEM_MemRead<=1'b0;
    EXE2MEM_MemWrite<=1'b0;
    EXE2MEM_Branch<=1'b0;
    EXE2MEM_MemtoReg<=1'b0;
    EXE2MEM_RegWrite<=1'b0;
end
else if(FlushEXE)
begin
    EXE2MEM_MemRead<=1'b0;
    EXE2MEM_MemWrite<=1'b0;
    EXE2MEM_Branch<=1'b0;
    EXE2MEM_MemtoReg<=1'b0;
    EXE2MEM_RegWrite<=1'b0;
end
else
begin
    EXE2MEM_MemRead<=ID2EXE_MemRead;
    EXE2MEM_MemWrite<=ID2EXE_MemWrite;
    EXE2MEM_Branch<=ID2EXE_Branch;
    EXE2MEM_MemtoReg<=ID2EXE_MemtoReg;
    EXE2MEM_RegWrite<=ID2EXE_RegWrite;
end

always@(posedge clk,posedge rst)
if(rst)
begin
    EXE2MEM_ALUOut<=32'd0;
    EXE2MEM_RegRd<=5'd0;
    EXE2MEM_Rt<=32'd0;
    EXE2MEM_BranchPC<=32'd0;
    EXE2MEM_NPC<=32'd0;
end
else
begin
    EXE2MEM_RegRd<=(ID2EXE_RegDst)?ID2EXE_rd:ID2EXE_rt;
    EXE2MEM_Rt<=ALUSrcB;               //ID2EXE_Rt or forwarded from EXE2MEM or forwarded from MEM2WB
    EXE2MEM_BranchPC<=ID2EXE_NPC+(ID2EXE_Imm<<2);
    EXE2MEM_NPC<=ID2EXE_NPC;
    case(ID2EXE_ALUOp)
        2'b00:EXE2MEM_ALUOut<=ALUSrcA+ID2EXE_Imm;          //lw or sw
        2'b01:EXE2MEM_ALUOut<=(ALUSrcA!=ALUSrcB)?1:0;
        2'b10:
        case (ID2EXE_Imm[5:0])
            6'b100000:EXE2MEM_ALUOut<=ALUSrcA+ALUSrcB;
            6'b100010:EXE2MEM_ALUOut<=ALUSrcA-ALUSrcB;
            6'b100100:EXE2MEM_ALUOut<=ALUSrcA&ALUSrcB;
            6'b100101:EXE2MEM_ALUOut<=ALUSrcA|ALUSrcB;
            6'b101010:EXE2MEM_ALUOut<=(ALUSrcA<ALUSrcB)?1:0;
        default: EXE2MEM_ALUOut<=EXE2MEM_ALUOut;
        endcase
        default:
            EXE2MEM_ALUOut<=EXE2MEM_ALUOut;
    endcase
end

//MEM
always@(posedge clk,posedge rst)
if(rst)
begin
    MEM2WB_RegWrite<=1'b0;
    MEM2WB_MemtoReg<=1'b0;
end
else
begin
    MEM2WB_RegWrite<=EXE2MEM_RegWrite;
    MEM2WB_MemtoReg<=EXE2MEM_MemtoReg;
end

always@(posedge clk,posedge rst)
if(rst)
begin
    MEM2WB_LDM<=32'd0;
    MEM2WB_ALUOut<=32'd0;
    MEM2WB_RegRd<=5'd0;
end
else
begin
    MEM2WB_ALUOut<=EXE2MEM_ALUOut;
    MEM2WB_RegRd<=EXE2MEM_RegRd;
    if(EXE2MEM_MemRead)
        MEM2WB_LDM<=DMEM[EXE2MEM_ALUOut];
    else if(EXE2MEM_MemWrite)
        DMEM[EXE2MEM_ALUOut]<=EXE2MEM_Rt;
end

//WB
always@(negedge clk,posedge rst)
if(rst)
    ;
else if(MEM2WB_RegWrite)
    if(MEM2WB_MemtoReg)
        RegFile[MEM2WB_RegRd]<=MEM2WB_LDM;
    else
        RegFile[MEM2WB_RegRd]<=MEM2WB_ALUOut;
        
endmodule

BTB代碼：

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/09/11 19:02:52
// Design Name: 
// Module Name: BTB
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module BTB(
input  clk, rst,

input [31:0] rd_PC,					//輸入PC
output reg rd_predicted,			//對外輸出的信號, 表示rd_PC是跳轉指令，此時rd_predicted_PC是有效資料
output reg [31:0] rd_predicted_PC,	//從buffer中得到的預測PC
input wr_req,						//寫請求信號
input [31:0] wr_PC,					//要寫入的分支PC
input [31:0] wr_predicted_PC,		//要寫入的預測PC
input wr_predicted_state_bit		//要寫入的預測狀態位
    );
parameter BUFFER_ADDR_LEN=4;
parameter BUFFER_SIZE=1<<BUFFER_ADDR_LEN;
parameter TAG_LEN=32-BUFFER_ADDR_LEN-2;

reg [TAG_LEN-1:0] tag_pc [0:BUFFER_SIZE-1]; 
reg [31:0] predicted_pc [0:BUFFER_SIZE-1];
reg predicted_state [0:BUFFER_SIZE-1];

wire [TAG_LEN-1:0] rd_pc_tag;
wire [BUFFER_ADDR_LEN-1:0] rd_pc_index;
wire [1:0] rd_pc_offset;
wire [TAG_LEN-1:0] wr_pc_tag;
wire [BUFFER_ADDR_LEN-1:0] wr_pc_index;
wire [1:0] wr_pc_offset;

assign {rd_pc_tag,rd_pc_index,rd_pc_offset}=rd_PC;
assign {wr_pc_tag,wr_pc_index,wr_pc_offset}=wr_PC;

always@(*)
if(tag_pc[rd_pc_index]==rd_pc_tag&&predicted_state[rd_pc_index]==1'b1)
    rd_predicted=1'b1;
else
    rd_predicted=1'b0;

always@(*)
   rd_predicted_PC=predicted_pc[rd_pc_index];

//write buffer,update
integer i;
always@(posedge clk,posedge rst)
if(rst)
begin
    for(i=0;i<BUFFER_SIZE;i=i+1)
    begin
        tag_pc[i]<=0;
        predicted_pc[i]<=0;
        predicted_state[i]<=0;
    end
end
else if(wr_req)
begin
    tag_pc[wr_pc_index]<=wr_pc_tag;
    predicted_pc[wr_pc_index]<=wr_predicted_PC;
    predicted_state[wr_pc_index]<=wr_predicted_state_bit;
end
endmodule

其余模塊代碼見鏈接
之前的MIPS代碼有問題，在更新PC時，若預測錯誤，則PC更新為新的跳轉地址的優先級應該高于因load-use資料冒險而產生的阻塞（Stall），現代碼更改如下：

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/07/23 15:31:35
// Design Name: 
// Module Name: MIPS
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module MIPS(
input clk,
input rst
    );
reg [31:0] RegFile [0:31];
reg [31:0] IMEM [0:255];
reg [31:0] DMEM [0:255];

integer i;
initial
begin
    for(i=0;i<256;i=i+1)
        DMEM[i]=i;
end

initial
begin
    for(i=0;i<32;i=i+1)
        RegFile[i]<=i;
end

initial
begin
    IMEM[0]=32'h8c810004;
    IMEM[4]=32'h00211820;
    IMEM[8]=32'h00c23022;
    IMEM[12]=32'h10c0fffc;
    IMEM[16]=32'h012a4020;
    IMEM[20]=32'h01ac5822;
    IMEM[24]=32'h01f07020;
end

wire IF2ID_Write;
wire PCWrite;
wire ID2EXE_Stall;
wire [31:0]ALUSrcA;                  
wire [31:0]ALUSrcB;
wire [1:0]ForwardA;
wire [1:0]ForwardB;
wire [4:0]IF2ID_rs;
wire [4:0]IF2ID_rt;
wire [31:0]MEM2WB_Data;
wire FlushIF;
wire FlushID;
wire FlushEXE;

assign FlushIF=(EXE2MEM_Branch==1'b1&&(EXE2MEM_ALUOut!=EXE2MEM_predicted))?1'b1:1'b0;           //若預測錯誤，則flush之前的3條指令
assign FlushID=(EXE2MEM_Branch==1'b1&&(EXE2MEM_ALUOut!=EXE2MEM_predicted))?1'b1:1'b0;
assign FlushEXE=(EXE2MEM_Branch==1'b1&&(EXE2MEM_ALUOut!=EXE2MEM_predicted))?1'b1:1'b0;

reg wr_req;
reg [31:0]wr_PC;
reg [31:0]wr_predicted_PC;
reg wr_predicted_state_bit;
reg [31:0]rd_PC;

wire rd_predicted_PC;
wire rd_predicted;

reg IF2ID_predicted;
reg ID2EXE_predicted;
reg EXE2MEM_predicted;


//更新BTB
always@(*)
if(EXE2MEM_Branch)
    if(EXE2MEM_ALUOut==1'b0&&EXE2MEM_predicted==1'b1)     //預測taken但不taken
    begin
        wr_req=1'b1;
        wr_PC=EXE2MEM_NPC-32'd4;
        wr_predicted_PC=EXE2MEM_BranchPC;
        wr_predicted_state_bit=1'b0;
    end
    else if(EXE2MEM_ALUOut==1'b1&&EXE2MEM_predicted==1'b0)    //預測不taken但taken
    begin
        wr_req=1'b1;
        wr_PC=EXE2MEM_NPC-32'd4;
        wr_predicted_PC=EXE2MEM_BranchPC;
        wr_predicted_state_bit=1'b1;
    end
    else
    begin
        wr_req=1'b0;
        wr_PC=EXE2MEM_NPC-32'd4;
        wr_predicted_PC=EXE2MEM_BranchPC;
        wr_predicted_state_bit=1'b0;
    end
else
begin
    wr_req=1'b0;
    wr_PC=EXE2MEM_NPC-32'd4;
    wr_predicted_PC=EXE2MEM_BranchPC;
    wr_predicted_state_bit=1'b0;
end
//傳遞rd_predicted,即預測結果，以與之后的實際結果相比較
always@(posedge clk,posedge rst)
if(rst)
begin
    IF2ID_predicted<=1'b0;
    ID2EXE_predicted<=1'b0;
    EXE2MEM_predicted<=1'b0;
end
else
begin
    IF2ID_predicted<=rd_predicted;
    ID2EXE_predicted<=IF2ID_predicted;
    EXE2MEM_predicted<=ID2EXE_predicted;
end


//IF
reg [31:0] PC;
reg [31:0] IF2ID_NPC;
reg [31:0] IF2ID_IR;
//ID
reg [4:0]ID2EXE_rs;                //Rs暫存器號 約定大寫為資料，小寫為暫存器�?
reg [4:0]ID2EXE_rt;                //Rt暫存器號
reg [4:0]ID2EXE_rd;                //Rd暫存器號
reg [31:0]ID2EXE_Rs;               //Rs暫存器內�?
reg [31:0]ID2EXE_Rt;               //Rt暫存器內�?
reg [31:0]ID2EXE_Imm;              //符號擴展后的立即�?
reg [31:0]ID2EXE_NPC;                  

reg ID2EXE_RegDst;
reg ID2EXE_ALUSrc;
reg ID2EXE_MemRead;
reg ID2EXE_MemWrite;
reg ID2EXE_Branch;
reg ID2EXE_MemtoReg;
reg ID2EXE_RegWrite;
reg [1:0] ID2EXE_ALUOp;
//EXE
reg [31:0]EXE2MEM_ALUOut;
reg [31:0]EXE2MEM_BranchPC;
reg [31:0]EXE2MEM_Rt;
reg [4:0]EXE2MEM_RegRd;                    //WB階段寫暫存器�?

reg EXE2MEM_MemRead;
reg EXE2MEM_MemWrite;
reg EXE2MEM_Branch;
reg EXE2MEM_MemtoReg;
reg EXE2MEM_RegWrite;
reg [31:0]EXE2MEM_NPC;
//MEM
reg [31:0]MEM2WB_LDM;
reg [31:0]MEM2WB_ALUOut;
reg [4:0]MEM2WB_RegRd;

reg MEM2WB_RegWrite;
reg MEM2WB_MemtoReg;

/****************************************************************************************/

assign IF2ID_rs=IF2ID_IR[25:21];
assign IF2ID_rt=IF2ID_IR[20:16];
assign MEM2WB_Data=(MEM2WB_MemtoReg)?MEM2WB_LDM:MEM2WB_ALUOut;

//IF
BTB V(
.clk(clk),
.rst(rst),
.rd_PC(PC),
.rd_predicted(rd_predicted),
.rd_predicted_PC(rd_predicted_PC),
.wr_req(wr_req),
.wr_PC(wr_PC),
.wr_predicted_PC(wr_predicted_PC),
.wr_predicted_state_bit(wr_predicted_state_bit)
);

always@(posedge clk,posedge rst)
begin
if(rst)
begin
    PC<=32'd0;
    IF2ID_NPC<=32'd0;
    IF2ID_IR<=32'd0;
end
else
begin
    if(EXE2MEM_Branch)
        if(EXE2MEM_predicted==1'b1&&EXE2MEM_ALUOut==1'b0)           //預測taken但實際沒tabke
            PC<=EXE2MEM_NPC;
        else if(EXE2MEM_predicted==1'b0&&EXE2MEM_ALUOut==1'b1)      //預測not taken但實際taken
            PC<=EXE2MEM_BranchPC;
        else if(PCWrite==1'b0)
            PC<=PC;
        else if(rd_predicted)
            PC<=rd_predicted_PC;
        else
            PC<=PC+32'd4;
    else if(PCWrite==1'b0)
        PC<=PC;
    else if(rd_predicted)
        PC<=rd_predicted_PC;
    else
        PC<=PC+32'd4;
    //
    if(FlushIF)
    begin
        IF2ID_NPC<=32'd0;
        IF2ID_IR<=32'd0;
    end
    else if(IF2ID_Write)
    begin
        IF2ID_NPC<=PC+4;
        IF2ID_IR<=IMEM[PC];
    end
    
    else
    begin
        IF2ID_NPC<=IF2ID_NPC;
        IF2ID_IR<=IF2ID_IR;
    end
end
end

//ID
HAZARD_DETECTION U1(
.ID2EXE_MemRead(ID2EXE_MemRead),
.IF2ID_rs(IF2ID_rs),
.IF2ID_rt(IF2ID_rt),
.ID2EXE_rt(ID2EXE_rt),
.PCWrite(PCWrite),
.ID2EXE_Stall(ID2EXE_Stall),
.IF2ID_Write(IF2ID_Write)
);

always@(posedge clk,posedge rst)
if(rst)
begin
    ID2EXE_RegDst<=1'b0;
    ID2EXE_ALUSrc<=1'b0;
    ID2EXE_ALUOp<=2'b00;
    ID2EXE_MemRead<=1'b0;
    ID2EXE_MemWrite<=1'b0;
    ID2EXE_Branch<=1'b0;
    ID2EXE_RegWrite<=1'b0;
    ID2EXE_MemtoReg<=1'b0;
end
else if(ID2EXE_Stall||FlushID)
begin
    ID2EXE_RegDst<=1'b0;
    ID2EXE_ALUSrc<=1'b0;
    ID2EXE_ALUOp<=2'b00;
    ID2EXE_MemRead<=1'b0;
    ID2EXE_MemWrite<=1'b0;
    ID2EXE_Branch<=1'b0;
    ID2EXE_RegWrite<=1'b0;
    ID2EXE_MemtoReg<=1'b0;
end
else
case(IF2ID_IR[31:26])
6'b000000:begin
    {ID2EXE_RegDst,ID2EXE_ALUSrc,ID2EXE_MemtoReg,ID2EXE_RegWrite,ID2EXE_MemRead,
    ID2EXE_MemWrite,ID2EXE_Branch,ID2EXE_ALUOp}<=9'b100100010;
end
6'b100011:begin
    {ID2EXE_RegDst,ID2EXE_ALUSrc,ID2EXE_MemtoReg,ID2EXE_RegWrite,ID2EXE_MemRead,
    ID2EXE_MemWrite,ID2EXE_Branch,ID2EXE_ALUOp}<=9'b011110000;
end
6'b101011:begin
    {ID2EXE_RegDst,ID2EXE_ALUSrc,ID2EXE_MemtoReg,ID2EXE_RegWrite,ID2EXE_MemRead,
    ID2EXE_MemWrite,ID2EXE_Branch,ID2EXE_ALUOp}<=9'b010001000;
end
6'b000100:begin
    {ID2EXE_RegDst,ID2EXE_ALUSrc,ID2EXE_MemtoReg,ID2EXE_RegWrite,ID2EXE_MemRead,
    ID2EXE_MemWrite,ID2EXE_Branch,ID2EXE_ALUOp}<=9'b000000101;
end
default:
    {ID2EXE_RegDst,ID2EXE_ALUSrc,ID2EXE_MemtoReg,ID2EXE_RegWrite,ID2EXE_MemRead,
    ID2EXE_MemWrite,ID2EXE_Branch,ID2EXE_ALUOp}<=9'b000000000;
endcase

always@(posedge clk,posedge rst)
if(rst)
begin
    ID2EXE_rs<=5'd0;
    ID2EXE_rt<=5'd0;
    ID2EXE_rd<=5'd0;
    ID2EXE_Rs<=32'd0;
    ID2EXE_Rt<=32'd0;
    ID2EXE_Imm<=32'd0;
    ID2EXE_NPC<=32'd0;
end
else if(FlushID)
begin
    ID2EXE_rs<=5'd0;
    ID2EXE_rt<=5'd0;
    ID2EXE_rd<=5'd0;
    ID2EXE_Rs<=32'd0;
    ID2EXE_Rt<=32'd0;
    ID2EXE_Imm<=32'd0;
    ID2EXE_NPC<=32'd0;
end
else
begin
    ID2EXE_rs<=IF2ID_IR[25:21];
    ID2EXE_rt<=IF2ID_IR[20:16];
    ID2EXE_rd<=IF2ID_IR[15:11];
    ID2EXE_Rs<=RegFile[IF2ID_IR[25:21]];
    ID2EXE_Rt<=RegFile[IF2ID_IR[20:16]];
    ID2EXE_Imm<={{16{IF2ID_IR[15]}},IF2ID_IR[15:0]};
    ID2EXE_NPC<=IF2ID_NPC;
end

//EXE

FORWARDING U2(
.ID2EXE_rs(ID2EXE_rs),
.ID2EXE_rt(ID2EXE_rt),
.EXE2MEM_RegRd(EXE2MEM_RegRd),
.MEM2WB_RegRd(MEM2WB_RegRd),
.EXE2MEM_RegWrite(EXE2MEM_RegWrite),
.MEM2WB_RegWrite(MEM2WB_RegWrite),
.ForwardA(ForwardA),
.ForwardB(ForwardB)
);
//ALUSrcA三�?�一
mux3_1 U3(
.a(ID2EXE_Rs),
.b(EXE2MEM_ALUOut),
.c(MEM2WB_Data),
.select(ForwardA),
.out(ALUSrcA)
);
//ALUSrcB
mux3_1 U4(
.a(ID2EXE_Rt),
.b(EXE2MEM_ALUOut),
.c(MEM2WB_Data),
.select(ForwardB),
.out(ALUSrcB)
);

always@(posedge clk,posedge rst)
if(rst)
begin
    EXE2MEM_MemRead<=1'b0;
    EXE2MEM_MemWrite<=1'b0;
    EXE2MEM_Branch<=1'b0;
    EXE2MEM_MemtoReg<=1'b0;
    EXE2MEM_RegWrite<=1'b0;
end
else if(FlushEXE)
begin
    EXE2MEM_MemRead<=1'b0;
    EXE2MEM_MemWrite<=1'b0;
    EXE2MEM_Branch<=1'b0;
    EXE2MEM_MemtoReg<=1'b0;
    EXE2MEM_RegWrite<=1'b0;
end
else
begin
    EXE2MEM_MemRead<=ID2EXE_MemRead;
    EXE2MEM_MemWrite<=ID2EXE_MemWrite;
    EXE2MEM_Branch<=ID2EXE_Branch;
    EXE2MEM_MemtoReg<=ID2EXE_MemtoReg;
    EXE2MEM_RegWrite<=ID2EXE_RegWrite;
end

always@(posedge clk,posedge rst)
if(rst)
begin
    EXE2MEM_ALUOut<=32'd0;
    EXE2MEM_RegRd<=5'd0;
    EXE2MEM_Rt<=32'd0;
    EXE2MEM_BranchPC<=32'd0;
    EXE2MEM_NPC<=32'd0;
end
else
begin
    EXE2MEM_RegRd<=(ID2EXE_RegDst)?ID2EXE_rd:ID2EXE_rt;
    EXE2MEM_Rt<=ALUSrcB;               //ID2EXE_Rt or forwarded from EXE2MEM or forwarded from MEM2WB
    EXE2MEM_BranchPC<=ID2EXE_NPC+(ID2EXE_Imm<<2);
    EXE2MEM_NPC<=ID2EXE_NPC;
    case(ID2EXE_ALUOp)
        2'b00:EXE2MEM_ALUOut<=ALUSrcA+ID2EXE_Imm;          //lw or sw
        2'b01:EXE2MEM_ALUOut<=(ALUSrcA!=ALUSrcB)?1:0;
        2'b10:
        case (ID2EXE_Imm[5:0])
            6'b100000:EXE2MEM_ALUOut<=ALUSrcA+ALUSrcB;
            6'b100010:EXE2MEM_ALUOut<=ALUSrcA-ALUSrcB;
            6'b100100:EXE2MEM_ALUOut<=ALUSrcA&ALUSrcB;
            6'b100101:EXE2MEM_ALUOut<=ALUSrcA|ALUSrcB;
            6'b101010:EXE2MEM_ALUOut<=(ALUSrcA<ALUSrcB)?1:0;
        default: EXE2MEM_ALUOut<=EXE2MEM_ALUOut;
        endcase
        default:
            EXE2MEM_ALUOut<=EXE2MEM_ALUOut;
    endcase
end

//MEM
always@(posedge clk,posedge rst)
if(rst)
begin
    MEM2WB_RegWrite<=1'b0;
    MEM2WB_MemtoReg<=1'b0;
end
else
begin
    MEM2WB_RegWrite<=EXE2MEM_RegWrite;
    MEM2WB_MemtoReg<=EXE2MEM_MemtoReg;
end

always@(posedge clk,posedge rst)
if(rst)
begin
    MEM2WB_LDM<=32'd0;
    MEM2WB_ALUOut<=32'd0;
    MEM2WB_RegRd<=5'd0;
end
else
begin
    MEM2WB_ALUOut<=EXE2MEM_ALUOut;
    MEM2WB_RegRd<=EXE2MEM_RegRd;
    if(EXE2MEM_MemRead)
        MEM2WB_LDM<=DMEM[EXE2MEM_ALUOut];
    else if(EXE2MEM_MemWrite)
        DMEM[EXE2MEM_ALUOut]<=EXE2MEM_Rt;
end

//WB
always@(negedge clk,posedge rst)
if(rst)
    ;
else if(MEM2WB_RegWrite)
    if(MEM2WB_MemtoReg)
        RegFile[MEM2WB_RegRd]<=MEM2WB_LDM;
    else
        RegFile[MEM2WB_RegRd]<=MEM2WB_ALUOut;
        
endmodule

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