1、Terms and Abbreviations

2、Introduction

本系列博客檔案準備轉譯通用中斷控制器體系結構的第3版（GICv3）手冊，它主要面向為ARMv8-A撰寫代碼的軟體工程師，

GIC 的全稱為 General Interrupt Controller，主要作用可以歸結為：接受硬體中斷信號并進行簡單處理，通過一定的設定策略，分給對應的CPU進行處理，

本博文提供了GICv3功能的以軟體為中心的概述，并描述了GICv3兼容中斷控制器的操作，它也是一本關于如何配置用于裸機環境的GICv3中斷控制器，

詳細描述請參考 ARM? Generic Interrupt Controller Architecture Specification
GIC architecture version 3.0 and 4.0.

2.2 Brief history of the GIC architecture

3、GICv3 fundamentals

3.1.1 ARM 中斷型別

• SGI: Software Generated Interrupt，軟體產生中斷，中斷號是 0-15，通過向SGI暫存器寫數觸發，可用于CPU間的通信，比如時間同步，全域行程調度資訊等，每個 PE 都有這么多 SGI 號，The Redistributor provides the configuration settings for PPIs and SGIs.
• PPI: Private Peripheral Interrupt，私有外設中斷，中斷號是 16~31，這些中斷一般是發送給特定的CPU的，比如每個CPU有自己對應的 Generic Timer，產生的中斷信號就發送給這個特定的CPU進行處理，每個 PE 都有這么多 PPI 號，The Redistributor provides the configuration settings for PPIs and SGIs.
• SPI: Shared Peripheral Interrupt，共享外設中斷，中斷號是 32~1019，比如按鍵觸發一個中斷，手機觸摸屏觸發的中斷，共享的意思是說可以從多個 PE 中選擇一個發送處理，當然也可以指定發送給某個 PE，The Distributor provides the routing configuration for SPIs, and holds all the associated routing and priority information.
  特殊中斷號，1020-1023，這個在 GICv3 中用于指示特別的場景，例如給 EL3 的軟體使用，
  保留中斷號，1024-8191，
• LPI: Locality-specific Peripheral Interrupt，區域外設中斷，中斷號 >=8192 ，LPI 沒有 active or active and pending state，得到回應后由處理器自動轉入 inactive 狀態，LPIs are new in GICv3, and they are different to the other types of interruptin a number of ways . In particular, LPIs are always message-based interrupts,and their configuration is held in tables in memory rather than registers. NOTE: LPIs are only supported when GICD_CTLR.ARE_NS==1.

3.1.2 Interrupt Identifiers

每個中斷源由一個ID號標識，稱為INTID，可用的
INTID分為多個范圍，每個范圍分配給一種特定型別的中斷，

### 3.1.3 How interrupts are signaled to the interrupt controller

傳統上，中斷是使用專用介面從外設向中斷控制器發送信號硬體信號，

GICv3支持此模型，另外還支持基于訊息的中斷，基于訊息的中斷是通過寫入中斷控制器中的暫存器來設定和清除的中斷，

使用一條訊息將中斷從外設轉發到中斷控制器將洗掉每個中斷源對專用信號的要求，這對于硬體來說是一個優勢大型系統的設計者，其中可能存在數百甚至數千個信號通過SoC布線，并在中斷控制器上會聚，在GICv3中，SPI可以是基于訊息的中斷，但LPI始終是基于訊息的中斷，不同的暫存器用于不同的中斷型別，如表4所示，
Impact of message-based interrupts on software

無論中斷是作為訊息發送還是使用專用信號發送，都不會對傳輸方式產生太大影響中斷處理代碼處理中斷，可能需要一些外圍設備的配置，例如，可能有必要指定中斷控制器的地址，

3.2 Interrupt state machine

中斷控制器為每個SPI、PPI和SGI中斷源維護一個狀態機，這

狀態機由四種狀態組成：

• In’a’ctive 不活躍的
  中斷源當前未斷言，

• Pending 掛起的
  中斷源已斷言，但中斷尚未確認PE首個被回應，

• Active 忙碌的
  中斷源已被斷言，中斷已被PE確認，

• Active and Pending 活動和掛起的
  中斷的一個實體已被確認，另一個實體正在掛起，

注意：LPI沒有活動或活動和掛起狀態，有

### 3.2.1 Level sensitive（電平觸發處理）
Inactive to Pending
An interrupt transitions from inactive to pending when the interrupt source is asserted.
At this point the GIC asserts the interrupt signal to the PE (if the interrupt is enabled and is of
sufficient priority).
Pending to Active & Pending
The interrupt transitions from pending to active and pending when a PE acknowledges the
interrupt by reading one of the IARs (Interrupt Acknowledge Registers) in the CPU interface. This
read is typically part of an interrupt handling routine that executes after an interrupt exception is
taken. However, software can also poll the IARs.
At this point the GIC deasserts the interrupt signal to the PE.
Active and Pending to Active
The interrupt transitions from active and pending to active when the peripheral de-asserts the
interrupt signal. This typically happens in response to the interrupt handling software that is
executing on the PE writing to a status register in the peripheral.
Active to Inactive
The interrupt goes from active to inactive when the PE writes to one of the EOIRs (End of
Interrupt Registers) in the CPU interface. This indicates that the PE has finished handling the
interrupt.

具體流程如下：

• 外部高電平中斷到達，中斷狀態置為pending狀態，
• 軟體讀取IAR暫存器，表示PE認可該中斷，但中斷依然為高，中斷狀態進入pending and active狀態，
• 軟體中斷處理完畢后，寫EOIR暫存器，表示優先級重置，過一段時間后，寫DIR暫存器，中斷狀態被置為idle狀態，

3.2.2 Edge-triggered（邊沿觸發處理）

Inactive to Pending
An interrupt transitions from inactive to pending when the interrupt source is asserted.
At this point the GIC asserts the interrupt signal to the PE (if the interrupt is enabled and is of
sufficient priority).
Pending to Active
The interrupt transitions from pending to active when a PE acknowledges the interrupt by reading
one of the IARs in the CPU interface. This read is typically part of an interrupt handling routine
that executes after an interrupt exception is taken. However, software can also poll the IARs.
At this point the GIC de-asserts the interrupt signal to the PE.
Active to Active and Pending
The interrupt goes from active to active and pending if the peripheral re-asserts the interrupt
signal.
Active and Pending to Pending
The interrupt goes from active and pending to pending when the PE writes to one of the EOIRs in
the CPU interface. This indicates that the PE has finished handling the first instance of the
interrupt.
At this point the GIC re-asserts the interrupt signal to the PE.

具體流程如下：

• 外部邊沿中斷到達，中斷狀態被置為pending狀態，
• 軟體讀取IAR暫存器值，表示PE認可該中斷，中斷狀態被置為active狀態，
• 軟體中斷處理完畢后，寫EOIR暫存器，表示優先級重置，過一段時間后，寫DIR暫存器，中斷狀態被置為idle狀態，

3.3 Affinity routing（親和路由）

GICv3使用關聯路由來識別連接的PE，并將中斷路由到特定PE或PEs組，PE的關聯性表示為四個8位欄位：
<affinity level 3>.<affinity level 2>.<affinity level 1>.<affinity level 0>

在關聯級別0上有一個重新分發器，每個重分發器都連接到一個CPU介面，再分配者控制SGI、PPI和LPI，見第4章，親和性方案與ARMv8-A中使用的方案相匹配，與中報告的PE的親和性相匹配MPIDR_EL1，系統設計者必須確保MPIDR_EL1指示的關聯值為與連接至PE的再分配器的GICR_TYPE3指示的相同，不同親和力級別的確切含義由特定處理器和SoC定義，

以下是一些例子：
. ..
...

在一個實作中不太可能存在所有可能的節點，例如，一個移動設備的SoC可以具有類似以下布局：
0.0.0.[0:3] Cores 0 to 3 of a Cortex-A53 processor
0.0.1.[0:1] Cores 0 to 1 of a Cortex-A57 processor

In ARMv8-A, AArch64 state supports four levels of affinity. AArch32 state, and ARMv7, can
only support three levels of affinity. This means a design that uses AArch32 state is limited to a
single node at affinity level 3 (0.x.y.z). GICD_TYPER.A3V indicates whether the interrupt
controller can support multiple level 3 nodes.
NOTE: Although each level 1 node can host up to 256 Redistributors at level 0, in practice it is
likely to be 16 or fewer. This is because of the way the target PEs for an SGI are encoded, as
described in Chapter 7.

在ARMv8-A中，AArch64狀態支持四個級別的關聯，AArch32狀態和ARMv7可以僅支持三個級別的關聯，這意味著使用AArch32狀態的設計僅限于關聯級別為3（0.x.y.z）的單個節點，GICD_TYPER.A3V表示中斷是否中斷控制器可以支持多個級別3節點，

注意：盡管每個級別1節點在級別0上最多可以承載256個重分發器，但實際上是這樣的可能是16個或更少，這是由于SGI的目標PE的編碼方式，

3.4 Security model

GICv3體系結構支持ARM信任區技術，必須為每個INTID分配一個組和安全設定，GICv3支持三種組合，如表5所示，

Group 0中斷始終以FIQ的形式發出信號，Group 1中斷信號為IRQ或FIQ取決于PE的當前安全狀態和例外級別，
這些規則旨在補充ARMv8-A安全狀態和例外級別路由控制，圖8顯示了一個簡化的軟體堆疊，以及不同型別的在EL0執行時發出中斷信號：

在本例中，IRQ路由到EL1（SCR_EL3.IRQ0），而FIQ路由到EL3（SCR_EL3.FIQ1），給定表6中描述的規則，在EL1或EL0執行時當前安全狀態的第1組中斷被視為IRQ，另一個安全狀態的中斷觸發FIQ，例外被帶到EL3，這然后允許在EL3執行的軟體執行必要的背景關系切換，

3.4.1 Impact on software

配置中斷時，軟體控制INTID到中斷組的分配控制器，只有在安全狀態下執行的軟體才能將INTID分配給中斷組，

通常，只有在安全狀態下執行的軟體才能訪問的設定和狀態安全中斷（Group 0和安全Group 1），

可以啟用從非安全狀態到安全中斷設定和狀態的訪問，這是使用GICD_NSACRn和GICR_NSACR暫存器分別控制每個INTID，

注：復位時INTID所屬的中斷組由實作定義，
注：LPI始終被視為非安全的第1組中斷，

3.4.2 Support for single Security state（支持單一安全狀態）

Support for two Security states is OPTIONAL in ARMv8-A and GICv3. An implementation can
choose to implement only a single Security state or two Security states.

In a GICv3 implementation that supports two Security states, one Security state can be disabled.
This is controlled by GICD_CTLR.DS.

GICD_CTLR.DS == 0
Two Security states (Secure and Non-secure) are supported

GICD_CTLR.DS == 1
Only a single Security state is supported. On implemenations that only implement a
single Security state, this bit is RAO/WI.

3.5 Programmers’ model

The register interface of a GICv3 interrupt controller is split into three groups:

• Distributor interface.
• Redistributor interface.
• CPU interface.
  Distributor (GICD_*)

The Distributor registers are memory-mapped, and contain global settings that affect all PEs
connected to the interrupt controller. The Distributor provides a programming interface for:
Interrupt prioritization and distribution of SPIs.

• Enabling and disabling SPIs.
• Setting the priority level of each SPI.
• Routing information for each SPI.
• Setting each SPI to be level-sensitive or edge-triggered.
• Generating message-based SPIs.
• Controlling the active and pending state of SPIs.
• Controls to determine the programmers’ model that is used in each Security state (affinity
  routing or legacy).

Distributor (GICD_*)

For each connected PE there is a Redistributor. The Redistributors provides a programming
interface for:

• Enabling and disabling SGIs and PPIs.
• Setting the priority level of SGIs and PPIs.
• Setting each PPI to be level-sensitive or edge-triggered.
• Assigning each SGI and PPI to an interrupt group.
• Controlling the state of SGIs and PPIs.
• Base address control for the data structures in memory that support the associated interrupt properties and pending state for LPIs.
  Power management support for the connected PE.

CPU interfaces (ICC_*_ELn)
Each Redistributor is connected to a CPU interface. The CPU interface provides a programming
interface for:

• General control and configuration to enable interrupt handling.
• Acknowledging an interrupt.
• Performing a priority drop and deactivation of interrupts.
• Setting an interrupt priority mask for the PE.
• Defining the preemption policy for the PE.
• Determining the highest priority pending interrupt for the PE.

在GICv3中，CPU介面暫存器作為系統暫存器（ICC）訪問，在使用這些暫存器之前，軟體必須啟用系統暫存器介面，這是可控的通過ICC_SRE_ELn暫存器中的SRE位，其中“n”指定例外級別（EL1）-EL3），

注：在GICv1和GICv2中，CPU介面暫存器為記憶體映射（GICC_*），
注：軟體可以通過讀取ID_AA64PFR0_EL1來檢查GIC系統暫存器支持
PE，請參閱ARM?體系結構參考手冊，ARMv8，了解有關的ARMv8-A體系結構組態檔
細節，